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| 型號： | AM42DL6402G85IT |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 2 Mbit (128 K x 16-Bit) Static RAM |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA73 |
| 封裝： | 8 X 11.60 MM, FBGA-73 |
| 文件頁數(shù)： | 11/62頁 |
| 文件大?。?/td> | 471K |
| 代理商： | AM42DL6402G85IT |
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10
Am42DL6402G
January 31, 2003
P R E L I M I N A R Y
MCP DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Tables 1-2 lists the device bus operations, the
inputs and control levels they require, and the result-
ing output. The following subsections describe each of
these operations in further detail.
Table 1.
Device Bus Operations—Flash Word Mode, CIOf = V
IH
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 11.5–12.5
V, V
HH
= 9.0 ± 0.5 V, X = Don’t Care, SADD = Flash Sector Address, A
IN
=
Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1.
Other operations except for those indicated in this column are inhibited.
2.
Do not apply CE#f = V
, CE1#s = V
IL
and CE2s = V
IH
at the same time.
3.
Don’t care or open LB#s or UB#s.
4.
If WP#/ACC = V
IL
, the boot sectors will be protected. If WP#/ACC = V
IH
the boot sectors protection will be removed.
If WP#/ACC = V
(9V), the program time will be reduced by 40%.
5.
The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection
and Unprotection” section.
6.
If WP#/ACC = V
, the two outermost boot sectors remain protected. If WP#/ACC = V
, the two outermost boot sector protection depends on
whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If WP#/ACC =
V
HH,
all sectors will be unprotected.
Operation
(Notes 1, 2)
CE#f
CE1#s
CE2s
OE#
WE#
Addr.
LB#s
UB#s
RESET#
WP#/ACC
(Note 4)
DQ7–
DQ0
DQ15–
DQ8
Read from Flash
L
H
X
L
H
A
IN
X
X
H
L/H
D
OUT
D
OUT
X
L
Write to Flash
L
H
X
H
L
A
IN
X
X
H
(Note 4)
D
IN
D
IN
X
L
Standby
V
±
0.3 V
H
X
X
X
X
X
X
V
±
0.3 V
H
High-Z
High-Z
X
L
Output Disable
L
L
H
H
H
X
L
X
H
L/H
High-Z
High-Z
H
H
X
X
L
Flash Hardware Reset
X
H
X
X
X
X
X
X
L
L/H
High-Z
High-Z
X
L
Sector Protect
(Note 5)
L
H
X
H
L
SADD,
A6 = L,
A1 = H,
A0 = L
X
X
V
ID
L/H
D
IN
X
X
L
Sector Unprotect (Note
5)
L
H
X
H
L
SADD,
A6 = H,
A1 = H,
A0 = L
X
X
V
ID
(Note 6)
D
IN
X
X
L
Temporary Sector
Unprotect
X
H
X
X
X
X
X
X
V
ID
(Note 6)
D
IN
High-Z
X
L
Read from SRAM
H
L
H
L
H
A
IN
L
L
H
X
D
OUT
D
OUT
H
L
High-Z
D
OUT
L
H
D
OUT
High-Z
Write to SRAM
H
L
H
X
L
A
IN
L
L
H
X
D
IN
D
IN
H
L
High-Z
D
IN
L
H
D
IN
High-Z
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