參數(shù)資料
型號: AM42DL6402G85IS
廠商: SPANSION LLC
元件分類: 存儲器
英文描述: 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 2 Mbit (128 K x 16-Bit) Static RAM
中文描述: SPECIALTY MEMORY CIRCUIT, PBGA73
封裝: 8 X 11.60 MM, FBGA-73
文件頁數(shù): 58/62頁
文件大?。?/td> 471K
代理商: AM42DL6402G85IS
January 31, 2003
Am42DL6402G
57
P R E L I M I N A R Y
SRAM AC CHARACTERISTICS
Notes:
1. UB#s and LB#s controlled, CIOs must be high.
2. t
CW
is measured from CE1#s going low to the end of write.
3. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CE1#s or WE# going high.
4. t
AS
is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (t
WP
) of low CE#1s and low WE#. A write begins when CE1#s goes low and WE# goes low
when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation.
A write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
WP
is measured from the beginning of write
to the end of write.
6. Output data may be present on the bus at this time; input signals should not be applied.
7. If OE# is high during the write cycle, the outputs will remain at high impedance.
Figure 33.
SRAM Write Cycle—UB#s and LB#s Control
Address
Data Valid
UB#s, LB#s
WE#
Data In
Data Out
High-Z
High-Z
t
WC
CE1#s
CE2s
t
AW
t
BW
t
DW
t
DH
t
WR
(See Note 3)
t
AS
(See Note 4)
t
CW
(See Note 2)
t
CW
(See Note 2)
t
WP
(See Note 5)
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