- 您現(xiàn)在的位置：買賣IC網 > PDF目錄375306 > AM42BDS640AGTC9IT (SPANSION LLC) LJT 13C 13#22D SKT RECP PDF資料下載
參數(shù)資料
| 型號： | AM42BDS640AGTC9IT |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | LJT 13C 13#22D SKT RECP |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA93 |
| 封裝： | 8 X 11.60 MM, FBGA-93 |
| 文件頁數(shù)： | 25/72頁 |
| 文件大?。?/td> | 1060K |
| 代理商： | AM42BDS640AGTC9IT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁
24
Am42BDS640AG
November 1, 2002
P R E L I M I N A R Y
Table 8.
Programmable Wait State Settings
Notes:
1. Upon power-up or hardware reset, the default setting is
seven wait states.
2. RDY will default to being active with data when the Wait
State Setting is set to a total initial access cycle of 2.
3. Assumes even address.
It is recommended that the wait state command
sequence be written, even if the default wait state value
is desired, to ensure the device is set as expected. A
hardware reset will set the wait state to the default set-
ting.
Handshaking Option
If the device is equipped with reduced wait-state hand-
shaking, the host system should set address bits
A14–A12 to 010 for a clock frequency of 40 MHz or to
011 for a clock frequency of 54 MHz for the
system/device to execute at maximum speed.
Table 9
describes the typical number of clock cycles
(wait states) for various conditions.
Table 9.
Initial Access Codes
* In the 8-, 16- and 32-word burst read modes, the address
pointer does not cross 64-word boundaries (addresses
which are multiples of 3Fh).
The autoselect function allows the host system to
determine whether the flash device is enabled for
reduced wait-state handshaking. See the “Autoselect
Command Sequence” section for more information.
Standard Handshaking Operation
For optimal burst mode performance on devices with
standard handshaking, the host system must set the
appropriate number of wait states in the flash device
depending on the clock frequency.
Table 10
describes the typical number of clock cycles
(wait states) for various conditions with A14–A12 set to
101.
Table 10.
Wait States for Standard Handshaking
* In the 8-, 16- and 32-word burst read modes, the address
pointer does not cross 64-word boundaries (addresses
which are multiples of 3Fh).
Burst Read Mode Configuration
The device supports four different burst read modes:
continuous mode, and 8, 16, and 32 word linear wrap
around modes. A continuous sequence begins at the
starting address and advances the address pointer
until the burst operation is complete. If the highest
address in the device is reached during the continuous
burst read mode, the address pointer wraps around to
the lowest address.
For example, an eight-word linear burst with wrap
around begins on the starting burst address written to
the device and then proceeds until the next 8 word
boundary. The address pointer then returns to the first
word of the boundary, wrapping back to the starting
location. The sixteen- and thirty-two linear wrap around
modes operate in a fashion similar to the eight-word
mode.
Table 11
shows the address bits and settings for the
four burst read modes.
A14
A13
A12
Total Initial Access
Cycles
0
0
0
2
0
0
1
3
0
1
0
4
0
1
1
5
1
0
0
6
1
0
1
7
System
Frequency
Range
E
O
E
w
O
w
Device
Speed
Rating
6–11 MHz
2
2
3
4
40 MHz
12–23 MHz
2
3
4
5
24–33 MHz
3
4
5
6
34–40 MHz
4
5
6
7
40–47 MHz
4
5
6
7
54 MHz
48–54 MHz
5
6
7
8
Conditions at Address
Typical No. of Clock
Cycles after AVD# Low
40/54 MHz
Initial address is even
7
Initial address is odd
7
Initial address is even,
and is at boundary crossing*
7
Initial address is odd,
and is at boundary crossing*
7
相關PDF資料 |
PDF描述 |
|---|---|
| AM42BDS640AGTD8IS | Circular Connector; No. of Contacts:13; Series:MS27468; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:11; Circular Contact Gender:Socket; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:11-35 RoHS Compliant: No |
| AM42BDS640AGTD8IT | Circular Connector; No. of Contacts:13; Series:MS27468; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:11; Circular Contact Gender:Socket; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:11-35 RoHS Compliant: No |
| AM42BDS640AGBD8IS | RES 93.1K-OHM 0.1% 0.125W 50PPM THIN-FILM SMD-1206 TR-7-PL ROHS |
| AM42BDS640AGBD8IT | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| AM42BDS640AGTD9IS | LJT 13C 13#22D SKT WALL RECP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM42BDS640AGTD8IS | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Burst Mode Flash Memory and 16 Mbit (1 M x 16-Bit) Static RAM |
| AM42BDS640AGTD8IT | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Burst Mode Flash Memory and 16 Mbit (1 M x 16-Bit) Static RAM |
| AM42BDS640AGTD9IS | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Burst Mode Flash Memory and 16 Mbit (1 M x 16-Bit) Static RAM |
| AM42BDS640AGTD9IT | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Burst Mode Flash Memory and 16 Mbit (1 M x 16-Bit) Static RAM |
| AM42DL1612DB30IS | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Am29DL16xD 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 2 Mbit (128 K x 16-Bit) Static RAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。