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參數(shù)資料
| 型號： | AM41DL6408G70IT |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
| 中文描述： | SPECIALTY MEMORY CIRCUIT, PBGA73 |
| 封裝： | 8 X 11.60 MM, FBGA-73 |
| 文件頁數(shù)： | 59/63頁 |
| 文件大?。?/td> | 1139K |
| 代理商： | AM41DL6408G70IT |
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58
Am41DL6408G
August 19, 2002
P R E L I M I N A R Y
AC CHARACTERISTICS
Notes:
1. UB#s and LB#s controlled, CIOs must be high.
2. t
CW
is measured from CE1#s going low to the end of write.
3. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CE1#s or WE# going high.
4. t
AS
is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (t
WP
) of low CE#1s and low WE#. A write begins when CE1#s goes low and WE# goes low
when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation.
A write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
WP
is measured from the beginning of write
to the end of write.
Figure 32.
SRAM Write Cycle—UB#s and LB#s Control
Address
Data Valid
UB#s, LB#s
WE#
Data In
Data Out
High-Z
High-Z
t
WC
CE1#s
CE2s
t
AW
t
BW
t
DW
t
DH
t
WR
(See Note 3)
t
AS
(See Note 4)
t
CW
(See Note 2)
t
CW
(See Note 2)
t
WP
(See Note 5)
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| AM42BDS640AGBC9IT | Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
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| AM42BDS640AGTC8IT | Circular Connector; No. of Contacts:13; Series:MS27468; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:11; Circular Contact Gender:Pin; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:11-35 RoHS Compliant: No |
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| AM41DL6408G85IT | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Package (MCP) Flash Memory and SRAM |
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