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參數(shù)資料
| 型號(hào)： | ALD4211SCL |
| 廠(chǎng)商： | Advanced Linear Devices Inc |
| 文件頁(yè)數(shù)： | 6/8頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC SW ANLG QUAD SPST 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 48 |
| 功能： | 開(kāi)關(guān) |
| 電路： | 4 x SPST - NC |
| 導(dǎo)通狀態(tài)電阻： | 365 歐姆 |
| 電壓電源： | 單/雙電源 |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 12 V，±1.5 V ~ 6 V |
| 電流 - 電源： | 10mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 管件 |
| 其它名稱(chēng)： | 1014-1156 |
2002 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FIN1108 Rev. 1.0.4
6
FIN
1108
—
LVD
S
8-
Port
,H
igh-
Speed
R
e
peat
er
AC Electrical Characteristics
Typical values are at TA=25°C with VCC=3.3V.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
tPLHD
Differential Output
Propagation Delay
LOW-to-HIGH
RL=100Ω, CL=5pF
VID=200mV to 450mV,
VIC= VID/2 to VCC – (VID/2)
Duty Cycle=50%
Figure 3
0.75
1.10
1.75
ns
tPHLD
Differential Output
Propagation Delay
HIGH-to-LOW
0.75
1.10
1.75
ns
tTLHD
Differential Output Rise
Time (20% to 80%)
0.29
0.40
0.58
ns
tTHLD
Differential Output Fall
Time (80% to 20%)
0.29
0.40
0.58
ns
tSK(P)
Pulse Skew
|tPLH - tPHL|
0.02
0.20
ns
tSK(LH)
Channel-to-Channel
Skew
(1)
0.02
0.15
ns
tSK(HL)
0.02
0.15
tSK(PP)
Part-to-Part Skew
(2)
0.5
ns
fMAX
Maximum Frequency
(3)(4)
400
>630
MHz
tPZHD
Differential Output
Enable Time from
Z to HIGH
RL=100Ω, CL=5pF
Figure 4, Figure 5
3.0
5.0
ns
tPZLD
Differential Output
Enable Time from
Z to LOW
3.1
5.0
ns
tPHZD
Differential Output
Disable Time from
HIGH to Z
2.2
5.0
ns
tPLZD
Differential Output
Disable Time from
LOW to Z
2.5
5.0
ns
tDJ
LVDS Data Jitter,
Deterministic
VID=300mV, PRBS=2
23-1,
VIC=1.2V at 800Mbps
80
135
ps
tRJ
LVDS Clock Jitter,
Random (RMS)
VID=300mV
VIC=1.2V at 400Mbps
1.9
3.5
ps
Notes:
1.
tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and
are switching in the same direction.
2.
tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two
devices switching in the same direction (either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with
the same supply voltage, same temperature, and have identical test circuits.
3.
Passing criteria for maximum frequency is the output VOD >250mV and the duty cycle is better than 45% / 55%
with all channels switching.
4.
Output loading is transmission-line environment only; CL is <1pF of stray test fixture capacitance.
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