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參數(shù)資料
| 型號(hào)： | ALC202 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:100; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:22; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:22-35 RoHS Compliant: No |
| 中文描述： | AC\u0026#39;97音頻編解碼器 |
| 文件頁數(shù)： | 16/29頁 |
| 文件大?。?/td> | 598K |
| 代理商： | ALC202 |
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Preliminary
Avance Logic, Inc.
ALC202
-
16 -
Rev0.62
http://www.realtek.com.tw
15:10
9
Reserved
GPIO1 Output Control
0: Drive GPIO1 low.
1: Drive GPIO1 high.
GPIO0 Output Control
0: Drive GPIO0 as low.
1: Drive GPIO0 as high.
Reserved
JD Interrupt Status (JD_IS)
0: Not JD interrupt.
1: JD interrupt.
JD_IS= (MX78.2==1)&(MX76.6==1) & (JD low-to-high transition).
Write 1 to clear this status bit.
GPIO1 Interrupt Status (GPIO1_IS). (When GPIO1 is used as input)
0: No GPIO1 interrupt.
1: GPIO1 interrupt.
GPIO1_IS= (MX76.1==0)&(MX76.5==1) & (GPIO1 low-to-high transition).
Write 1 to clear this status bit.
GPIO0 Interrupt Status (GPIO0_IS). (When GPIO0 is used as input)
0: No GPIO0 interrupt.
1: GPIO0 interrupt.
GPIO0_IS= (MX76.0==0)&(MX76.4==1) & (GPIO0 low-to-high transition)
Write 1 to clear this status bit.
Reserved
Jack-Detect Event (JDEVT)
0: No Jack-Detect event occurs.
1: Jack-Detect event occurs.
JDEVT = MX7A.0 & MX7A.1
GPIO1 Input Status
0: GPIO1 is driven low by external device (input).
1: GPIO1 is driven high by external device (input).
GPIO0 Input Status
0: GPIO0 is driven low by external device (input).
1: GPIO0 is driven high by external device (input).
GPIO interrupt (GPINT) in bit0 of SDATA_IN’s slot-12 =
(MX78.4 | MX78.5 | MX78.6).
When GPIO1/0 is used as input pin, its status will be also reflected in bit2/1 of SDIN’s slot-12. Once
GPIO1/0 is used as output pin, the bit2/1 of SDATA_IN’s slot-12 is always 0.
The GPIOx is internally pulled high by a weak resistor.
R/W
8
R/W
7
6
NA
R/W
5
R/W
4
R/W
3
2
NA
R
1
R
0
R
MX7A
Bit
Default: 57C0H
Type
R
Function
15
Clock Source Selection (XTLSEL)
0: 24.576MHz crystal is used. DPLL is bypass. (XTLSEL is floating or open)
1: 14.318MHz crystal is used. 14.318M
à
24.576M digital PLL is enabled.
(XTLSEL is pull low)
ENHPF, Digital high-pass filter to eliminate variation in DC offset.
0: Disable 1: Enable (default)
Reserved
Pin-48 Function Selection
0: S/PDIF output (default) 1: TEST
Output value of TEST (when bit-7 is set)
0: ADC CLK 1: DAC CLK
Pin-47 Function Selection
0: EAPD output (default) 1: Jack-Detect input
14
R/W
13:8
7
NA
R/W
6
R/W
5
R/W
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