參數(shù)資料
型號(hào): AL128
廠商: Electronic Theatre Controls, Inc.
元件分類: 圓形連接器
英文描述: Circular Connector; No. of Contacts:55; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:22; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No
中文描述: 即插即用VGA到的NTSC / PAL制式轉(zhuǎn)換器
文件頁數(shù): 34/45頁
文件大?。?/td> 498K
代理商: AL128
AL128
April 2, 1999
34
This register defines the horizontal total sampled pixels between 2 continuous input
horizontal sync. The actual number is defined as: PllDiv * 16
Make sure that the value of (Graphic Clock PLL divider) * (Detected Vertical Total) *
(Detected Scan Rate) does not exceed the maximum speed of the field memory used, e.g.,
PllDiv * 16 * GinVTotal * 4 * VGArr <= 56MHz for AL422
PllDiv, GinVTotal and VGArr are defined by registers 28h, 43h and 44h respectively.
2Bh:
Delta of Horizontal Start in Zoom Mode (R/W) [GINHSTZOOMDLT]
GinHStZoomDlt <6:0>
(unit: 8 pixels) ** X Pan (in zoom mode) **
<7>
Reserved
This does not apply to non-zoom mode.
The actual horizontal capture start position is defined as:
(default horizontal capture start position) + (GinHStZoomDlt * 8).
The value of GinHStZoomDlt is signed, and its range is between –64 and 63.
Please refer to Section 8.3, AL128 Plug & Play Hardware Table for the default horizontal
capture start positions.
2Ch:
Delta of Vertical Start in Zoom Mode (R/W) [GINVSTZOOMDLT]
GinVStZoomDlt <6:0>
(unit: 4 lines) ** Y Pan (in zoom mode) **
<7>
Reserved
This does not apply to non-zoom mode.
The actual vertical capture start position is defined as:
(default vertical capture start position) + (GinVStZoomDlt * 4).
The value of GinVStZoomDlt is signed, and its range is between -64 and 63.
Please refer to Section 8.3, AL128 Plug & Play Hardware Table for the default vertical
capture start positions.
33h:
Graphic Data Processing (R/W) [GRAPHDP]
VFltMode
<2:0>
UdScanX
<3>
Vertical Flicker filter mode select ** Filter modes **
H direction only underscan
This only reply to H/W default mode. For S/W mode, please
use reg#28h and reg#23h to control the horizontal sampling
and set this bit to 0
Reserved
Reserved
1: Underscan; 0: Overscan.
To disable the hardware default
settings of the underscan mode, program this bit as 0.
For S/W control, use reg#28h and reg#23h to control the
horizontal sampling and set this bit to 0
Reserved
<4>
<5>
<6>
SoftUdScan
<7>
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