參數(shù)資料
型號(hào): AGLP-EVAL-KIT
廠商: Microsemi SoC
文件頁數(shù): 9/27頁
文件大?。?/td> 0K
描述: KIT EVAL HARDWARE FOR AGLP
標(biāo)準(zhǔn)包裝: 1
系列: IGLOO PLUS
類型: FPGA
適用于相關(guān)產(chǎn)品: AGLP125
所含物品: 板,電纜,DVD,跳線,電源,編程器
其它名稱: 1100-1137
18 www.microsemi.com/soc
Axcelerator
500+MHzinternalperformance
500+MHzembeddedFIFOs
PLLoutputupto1GHzand
8PLLsperdevice
6levelsoflogicat156+MHz
1.5V,1.8V,2.5V,and3.3V
mixed-voltage operation
Bank-selectableI/Os—8banks
per chip
8globalclocksperdevice
4.5kbitsvariable-aspectRAM
blocks with built-in FIFO control
Secureprogrammingtechnology
is designed to prevent reverse
engineeringanddesigntheft
Axcelerator
Axcelerator Devices
I/Os Per Package
Axcelerator Device
AX125
AX250
AX500
AX1000
AX2000
PQ
208
BG
729
FG
256, 324
256, 484
484, 676
484, 676, 896
896, 1152
CQ
208, 352
352
256, 352
CG/LG
624
Firstforspeedandperformance
The Axcelerator FPGA family is a single-chip, nonvolatile solution offering high performance and unprecedented design security at densities of up to 2 million
equivalent system gates. Utilizing the AX architecture, Axcelerator devices have several system-level features, such as embedded SRAM (with embedded FIFO
control logic), PLLs, segmentable clocks, chip-wide highway routing, and carry logic. Based upon 0.15 m, seven-layers-of-metal CMOS antifuse process
technology, 350 MHz system performance.
Axcelerator Device
AX125
AX250
AX500
AX1000
AX2000
Capacity
(in equivalent system gates)
125,000
250,000
500,000
1,000,000
2,000,000
Typical Gates
82,000
154,000
286,000
612,000
1,060,000
Register(R-cells)
672
1,408
2,688
6,048
10,752
Combinatorial (C-cells)
1,344
2,816
5,376
12,096
21,504
Maximum Flip-Flops
1,344
2,816
5,376
12,096
21,504
NumberofCoreRAMBlocks
4
12
16
36
64
TotalBitsofCoreRAM
18,432
55,296
73,728
165,888
294,912
Clocks (hardwired)
4
Clocks (routed)
4
PLLs
8
I/OBanks
8
Maximum User I/Os
168
248
336
516
684
MaximumLVDSChannels
84
124
168
258
342
TotalI/ORegisters
504
744
1,008
1,548
2,052
Speed Grades
Std., –1, –2
Temperature Grades
C, I
C, I, M
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