2-10 Revision 13 Table 2-14 Summary of I/O Output Buffer Power (per pin) – Defaul" />
參數(shù)資料
型號: AGLE600V5-FGG484
廠商: Microsemi SoC
文件頁數(shù): 84/166頁
文件大?。?/td> 0K
描述: IC FPGA 1KB FLASH 600K 484-FBGA
標(biāo)準(zhǔn)包裝: 60
系列: IGLOOe
邏輯元件/單元數(shù): 13824
RAM 位總計: 110592
輸入/輸出數(shù): 270
門數(shù): 600000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 484-BGA
供應(yīng)商設(shè)備封裝: 484-FPBGA(23x23)
IGLOOe DC and Switching Characteristics
2-10
Revision 13
Table 2-14 Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1
CLOAD
(pF)
VCCI
(V)
Static Power
PDC7 (mW)2
Dynamic Power
PAC10 (W/MHz)3
Single-Ended
3.3 V LVTTL/LVCMOS
5
3.3
148.00
3.3 V LVCMOS Wide Range 4
5
3.3
148.00
2.5 V LVCMOS
5
2.5
83.23
1.8 V LVCMOS
5
1.8
54.58
1.5 V LVCMOS (JESD8-11)
5
1.5
37.05
1.2 V LVCMOS (JESD8-11)
5
1.2
17.94
1.2 V LVCMOS (JESD8-11) – Wide
Range
17.94
3.3 V PCI
10
3.3
204.61
3.3 V PCI-X
10
3.3
204.61
Voltage-Referenced
3.3 V GTL
10
3.3
24.08
2.5 V GTL
10
2.5
13.52
3.3 V GTL+
10
3.3
24.10
2.5 V GTL+
10
2.5
13.54
HSTL (I)
20
1.5
7.08
26.22
HSTL (II)
20
1.5
13.88
27.18
SSTL2 (I)
30
2.5
16.69
105.56
SSTL2 (II)
30
2.5
25.91
116.60
SSTL3 (I)
30
3.3
26.02
114.67
SSTL3 (II)
30
3.3
42.21
131.69
Differential
LVDS
2.5
7.70
89.62
LVPECL
3.3
19.42
167.86
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. PDC7 is the static power (where applicable) measured on VCCI.
3. PAC10 is the total dynamic power measured on VCCI.
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification.
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