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IGLOO Low Power Flash FPGAs
Revision 23
2-31
Table 2-33 Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade,
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI (per
standard)
Applicable to Standard I/O Banks
I/O
S
tan
dard
Dr
ive
S
trength)
Eq
uivalen
tSo
ft
ware
Default
Drive
S
trength
Option
1
(mA)
Slew
Rat
e
Ca
p
acitive
Lo
ad
(p
F)
Ex
te
rn
al
R
esi
st
or
(
)
t DO
UT
(ns)
t DP
(ns)
t DI
N
(ns)
t PY
(ns)
t EOUT
(ns)
t ZL
(ns)
t ZH
(ns)
t LZ
(ns)
t HZ
(ns)
Unit
s
3.3 V
LVTTL /
3.3 V
LVCMOS
8 mA
8
High
5
–
0.97 1.85 0.18 0.83 0.66 1.89 1.46 1.96 2.26
ns
3.3 V
LVCMOS
Wide
Range2
100 A
8
High
5
–
0.97 2.62 0.18 1.17 0.66 2.63 2.02 2.79 3.17
ns
2.5 V
LVCMOS
8 mA
8
High
5
–
0.97 1.88 0.18 1.04 0.66 1.92 1.63 1.95 2.15
ns
1.8 V
LVCMOS
4 mA
4
High
5
–
0.97 2.18 0.18 0.98 0.66 2.22 1.93 1.97 2.06
ns
1.5 V
LVCMOS
2 mA
2
High
5
–
0.97 2.51 0.18 1.14 0.66 2.56 2.21 1.99 2.03
ns
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 A. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.