Revision 23 2-41 Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor鈥揟ransistor " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AGL060V2-CS121
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 204/250闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 1KB FLASH 60K 121-CSP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 490
绯诲垪锛� IGLOO
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 1536
RAM 浣嶇附瑷�(j矛)锛� 18432
杓稿叆/杓稿嚭鏁�(sh霉)锛� 96
闁€鏁�(sh霉)锛� 60000
闆绘簮闆诲锛� 1.14 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 121-VFBGA锛孋SBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 121-CSP锛�6x6锛�
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IGLOO Low Power Flash FPGAs
Revision 23
2-41
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor鈥揟ransistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LVTTL input buffer and push-pull output buffer. Furthermore, all LVCMOS 3.3 V
software macros comply with LVCMOS 3.3 V wide range as specified in the JESD8a specification.
Table 2-47 Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH IOL IOH
IOSL
IOSH
IIL1 IIH2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
Max.
mA3
Max.
mA3
A4 A4
2 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
2
25
27
10 10
4 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
4
25
27
10 10
6 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
6
51
54
10 10
8 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
8
51
54
10 10
12 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
12 12
103
109
10 10
16 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
16 16
132
127
10 10
24 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
24 24
268
181
10 10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where 鈥�0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at 100掳C junction temperature and maximum voltage.
4. Currents are measured at 85掳C junction temperature.
5. Software default selection highlighted in gray.
Table 2-48 Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL1 IIH2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
Max.
mA3
Max.
mA3
A4 A4
2 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
2
25
27
10
4 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
4
25
27
10
6 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
6
51
54
10
8 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
8
51
54
10
12 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
12
103
109
10
16 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
16
103
109
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where 鈥�0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at 100掳C junction temperature and maximum voltage.
4. Currents are measured at 85掳C junction temperature.
5. Software default selection highlighted in gray.
鐩搁棞(gu膩n)PDF璩囨枡
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AGL060V2-CS121I 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 60K 121-CSP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪锛� 绯诲垪:IGLOO 妯�(bi膩o)婧�(zh菙n)鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:289-CSP锛�14x14锛�
AGL060V2-CS144 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
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AGL060V2-CS144PP 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
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