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鍨嬭櫉锛� AFS1500-FG676I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 55/334闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 8MB FLASH 1.5M 676-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 40
绯诲垪锛� Fusion®
RAM 浣嶇附瑷堬細 276480
杓稿叆/杓稿嚭鏁�(sh霉)锛� 252
闁€鏁�(sh霉)锛� 1500000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 100°C
灏佽/澶栨锛� 676-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 676-FBGA锛�27x27锛�
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Device Architecture
2-132
Revision 4
Analog Quad ACM Description
Table 2-56 maps out the ACM space associated with configuration of the Analog Quads within the
Analog Block. Table 2-56 shows the byte assignment within each quad and the function of each bit within
each byte. Subsequent tables will explain each bit setting and how it corresponds to a particular
configuration. After 3.3 V and 1.5 V are applied to Fusion, Analog Quad configuration registers are
loaded with default settings until the initialization and configuration state machine changes them to user-
defined settings.
Table 2-56 Analog Quad ACM Byte Assignment
Byte
Bit
Signal (Bx)
Function
Default Setting
Byte 0
(AV)
0
B0[0]
Scaling factor control 鈥� prescaler
Highest voltage range
1
B0[1]
2
B0[2]
3
B0[3]
Analog MUX select
Prescaler
4
B0[4]
Current monitor switch
Off
5
B0[5]
Direct analog input switch
Off
6
B0[6]
Selects V-pad polarity
Positive
7
B0[7]
Prescaler op amp mode
Power-down
Byte 1
(AC)
0
B1[0]
Scaling factor control 鈥� prescaler
Highest voltage range
1
B1[1]
2
B1[2]
3
B1[3]
Analog MUX select
Prescaler
4
B1[4]
5
B1[5]
Direct analog input switch
Off
6
B1[6]
Selects C-pad polarity
Positive
7
B1[7]
Prescaler op amp mode
Power-down
Byte 2
(AG)
0
B2[0]
Internal chip temperature monitor * Off
1
B2[1]
Spare
鈥�
2
B2[2]
Current drive control
Lowest current
3
B2[3]
4
B2[4]
Spare
鈥�
5
B2[5]
Spare
鈥�
6
B2[6]
Selects G-pad polarity
Positive
7
B2[7]
Selects low/high drive
Low drive
Byte 3
(AT)
0
B3[0]
Scaling factor control 鈥� prescaler
Highest voltage range
1
B3[1]
2
B3[2]
3
B3[3]
Analog MUX select
Prescaler
4
B3[4]
5
B3[5]
Direct analog input switch
Off
6
B3[6]
鈥�
7
B3[7]
Prescaler op amp mode
Power-down
Note: *For the internal temperature monitor to function, Bit 0 of Byte 2 for all 10 Quads must be set.
鐩搁棞(gu膩n)PDF璩囨枡
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鍙冩暩(sh霉)鎻忚堪
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AFS1500-FGG256I 鍔熻兘鎻忚堪:IC FPGA 8MB FLASH 1.5M 256-FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:Fusion® 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 鐗硅壊鐢�(ch菐n)鍝�:Cyclone? IV FPGAs 妯�(bi膩o)婧�(zh菙n)鍖呰:60 绯诲垪:CYCLONE® IV GX LAB/CLB鏁�(sh霉):9360 閭忚集鍏冧欢/鍠厓鏁�(sh霉):149760 RAM 浣嶇附瑷�:6635520 杓稿叆/杓稿嚭鏁�(sh霉):270 闁€鏁�(sh霉):- 闆绘簮闆诲:1.16 V ~ 1.24 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 85°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FBGA锛�23x23锛�
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