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Fusion Family of Mixed Signal FPGAs
Revision 4
2-203
2.5 V GTL
Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier
input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V.
Timing Characteristics
Table 2-141 Minimum and Maximum DC Input and Output Levels
2.5 GTL
VIL
VIH
VOL
VOH
IOL IOH IOSL IOSH IIL1
IIH2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
Max.
mA3
Max.
mA3
A4 A4
20 mA3
鈥�0.3
VREF 鈥� 0.05 VREF + 0.05
3.6
0.4
鈥�
20
124
169
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where 鈥�0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100掳C junction temperature) and maximum voltage.
4. Currents are measured at 85掳C junction temperature.
Figure 2-125 AC Loading
Table 2-142 AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
VREF 鈥� 0.05
VREF + 0.05
0.8
1.2
10
Note: *Measuring point = Vtrip. See Table 2-90 on page 2-169 for a complete table of trip points.
Test Point
10 pF
25
GTL
VTT
Table 2-143 2.5 V GTL
Commercial Temperature Range Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V, VREF = 0.8 V
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
Std.
0.66
2.13
0.04
2.46
0.43
2.16
2.13
4.40
4.36
ns
鈥�1
0.56
1.81
0.04
2.09
0.36
1.84
1.81
3.74
3.71
ns
鈥�2
0.49
1.59
0.03
1.83
0.32
1.61
1.59
3.28
3.26
ns
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on
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