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參數(shù)資料
| 型號(hào)： | AFE1115E |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:12; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:15-97 RoHS Compliant: No |
| 中文描述： | HDSL / MDSL模擬前端與石英振蕩器 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 219K |
| 代理商： | AFE1115E |
8
AFE1115
rxHYB AND rxLINE INPUT COMMON-MODE
OPTIONAL VOLTAGE
The AFE1115 will meet specifications with the application
circuit shown in the Basic Connection Diagram (Figure 2)
above. However, slightly improved performance may be
obtained with the Hybrid input (rxHYB) and the Line input
(rxLINE) set to a common mode voltage of 1.5V. The
negative reference output pin (vrREFN, pin 40) provides a
good 1.5V level to use to set the common-mode voltage.
The circuit shown in Figure 3 can be used to set the
common-mode voltage of the Line input to 1.5V.
A similar circuit can be used to set the Hybrid input to 1.5V.
Another option for the Hybrid input is to design the external
compromise hybrid so that the signal into the rsHYB inputs
is centered at 1.5V. If the compromise hybrid circuit is AC
coupled to the rxHYB inputs, an external pull-up resistor to
vrREFN may be needed to center the input at 1.5V.
375
2k
to vrREFN
(1.5V)
to Line
2k
0.1μF
100pF
AFE
375
rxLINE–
rxLINE+
0.1μF
FIGURE 3. Optional rxLINE Input Common-mode Voltage
Control.
FIGURE 4. Timing Diagram.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
Serial Clock Period
Serial Clock LOW
Serial Clock HIGH
Delay of 16th clock rising edge to falling edge of txCLK or vcLE
Dealy of txCLK or vcLE to the next rising edge of Serial Clock
txCLK or vcLE HIGH
txCLK or vcLE LOW
DATA setup time
DATA hold time
35
15
15
10
10
15
15
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
1
t
2
t
3
txSCLK
(tx serial clock)
TRANSMIT DATA TIMING
txCLK
(baud clock)
txDATA
(tx data input)
t
8
t
9
Bit 2
Bit 3
t
4
t
6
t
7
t
5
MSB
Bit 1
LSB
Bit 16
t
1
t
2
t
3
vcSCLK
(serial clock)
VCXO CONTROL TIMING
vcLE
(latch enable)
vcDATA
(data)
t
8
t
9
Bit 2
Bit 3
t
4
t
6
t
7
t
5
MSB
Bit 1
LSB
Bit 16
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PDF描述 |
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| AFE1124E | Circular Connector; No. of Contacts:15; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:15-15 RoHS Compliant: No |
| AFE1144 | Circular Connector; No. of Contacts:15; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:15-15 RoHS Compliant: No |
| AFE1144E | Circular Connector; No. of Contacts:15; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:15-15 RoHS Compliant: No |
| AFE1203 | Circular Connector; No. of Contacts:15; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:15-15 RoHS Compliant: No |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AFE1115E/1K | 功能描述:IC ANALOG FRONT END 56-SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AFE1115E-1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AFE1115E-1/1K | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AFE1124 | 制造商:BB 制造商全稱:BB 功能描述:HDSL/MDSL ANALOG FRONT END |
| AFE1124E | 功能描述:電信線路管理 IC HDSL/MDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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