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參數(shù)資料
| 型號： | AFE1105E |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:12; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:15-97 RoHS Compliant: No |
| 中文描述： | HDSL / MDSL模擬前端 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大小： | 206K |
| 代理商： | AFE1105E |
8
AFE1105
TIMING DIAGRAM
FIGURE 3. Timing Diagram.
RECEIVE TIMING
The rxSYNC signal controls portions of the A/D converter’s
decimation filter and the data output timing of the A/D
converter. It is generated at the symbol rate by the user and
must be synchronized with txCLK. The rising edge of
rxSYNC can occur at the falling edge of txCLK or it can be
shifted by the user in increments of 1/48 of a symbol period
to one of 47 discrete delay times after the falling edge of
txCLK.
The bandwidth of the A/D converter decimation filter is
equal to one half of the symbol rate. The A/D converter data
output rate is 2X the symbol rate. The specifications of the
AFE1105 assume that one A/D converter output is used per
symbol period and the other interpolated output is ignored.
The Receive Timing Diagram above suggests using the
rxSYNC pulse to read the first data output in a symbol
period. Either data output may be used. Both data outputs
may be used for more flexible post-processing.
t
tx1
t
tx2
t
tx1
/4
t
tx1
/2
(n + 25.5) t
tx1
/48
(n + 1.5) t
tx1
/48
Data 1
Data 1a
Data 2
3t
tx1
/4
txCLK
Transmit Timing
txDAT
(+3 Symbol)
txDAT (+1 Symbol)
txDAT (–1 Symbol)
txDAT (–3 Symbol)
rxSYNC
Receive Timing
rxD13 - rxD0
t
/24 min
nt
tx1
/48± t
tx1
/96
20ns
20ns
NOTES: (1) Any transmit sequence not shown will result in a zero symbol. (2) All transitions are specified relative to the falling edge of
txCLK. (3) Maximum allowable error for any txDAT edge is ±t
/12 (±17.8ns at E1 rate; ±26.6ns at T1 rate). (4) Both txDAT inputs are
read by the AFE1103 at 1/8, 3/8, and 5/8 of a symbol period from the rising edge of txCLK. (5) rxSYNC can shift to one of 48 discrete
delay times from the falling edge of txCLK. (6) It is recommended that rxD13 - rxD0 be read on the rising edge of rxSYNC.
20ns
20ns
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| AFE1115 | Circular Connector; No. of Contacts:12; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:15-97 RoHS Compliant: No |
| AFE1115E | Circular Connector; No. of Contacts:12; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:15-97 RoHS Compliant: No |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AFE1105E/1K | 功能描述:電信線路管理 IC HDSL/MDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE1105E/1KG4 | 功能描述:電信線路管理 IC HDSL/MDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE1105EG4 | 功能描述:電信線路管理 IC HDSL/MDSL Analog Front End RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE1115 | 制造商:BB 制造商全稱:BB 功能描述:HDSL/MDSL ANALOG FRONT END WITH VCXO |
| AFE1115E | 功能描述:IC ANALOG FRONT END 56-SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據采集 - 模擬前端 (AFE) 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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