參數(shù)資料
型號： ADZS-BF537-ASKIT
廠商： Analog Devices Inc
文件頁數(shù)： 66/68頁
文件大?。?/td> 0K
描述： BOARD EVAL SKIT ADSP-BF537
產(chǎn)品培訓模塊： Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
標準包裝： 1
系列： Blackfin®
類型： DSP：音頻
適用于相關產(chǎn)品： ADSP-BF537
所含物品： 板
相關產(chǎn)品： ADSP-BF537KBCZ-6BV-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537BBCZ-5BV-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537KBCZ-6AV-ND - IC DSP CTLR 16BIT 182CSPBGA
ADSP-BF537BBCZ-5AV-ND - IC DSP CTLR 16BIT 182CSPBGA
ADSP-BF537BBCZ-5B-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537BBC-5A-ND - IC DSP CTLR 16BIT 182CSPBGA
Rev. J
|
Page 7 of 68
|
February 2014
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority
interrupts (IVG15–14) are recommended to be reserved for
software interrupt handlers, leaving seven prioritized interrupt
inputs to support the peripherals of the Blackfin processor.
Table 2 describes the inputs to the CEC, identifies their names
in the event vector table (EVT), and lists their priorities.
System Interrupt Controller (SIC)
The system interrupt controller provides the mapping and rout-
ing of events from the many peripheral interrupt sources to the
prioritized general-purpose interrupt inputs of the CEC.
Although the processor provides a default mapping, the user
can alter the mappings and priorities of interrupt events by writ-
ing the appropriate values into the interrupt assignment
registers (IAR). Table 3 describes the inputs into the SIC and the
default mappings into the CEC.
Table 2. Core Event Controller (CEC)
Priority
(0 Is Highest)
Event Class
EVT Entry
0Emulation/Test Control
EMU
1Reset
RST
2
Nonmaskable Interrupt
NMI
3Exception
EVX
4Reserved
—
5
Hardware Error
IVHW
6
Core Timer
IVTMR
7
General-Purpose Interrupt 7
IVG7
8
General-Purpose Interrupt 8
IVG8
9
General-Purpose Interrupt 9
IVG9
10
General-Purpose Interrupt 10
IVG10
11
General-Purpose Interrupt 11
IVG11
12
General-Purpose Interrupt 12
IVG12
13
General-Purpose Interrupt 13
IVG13
14
General-Purpose Interrupt 14
IVG14
15
General-Purpose Interrupt 15
IVG15
Table 3. System Interrupt Controller (SIC)
Peripheral Interrupt Event
Default
Mapping
Peripheral
Interrupt ID
PLL Wakeup
IVG7
0
DMA Error (Generic)
IVG7
1
DMAR0 Block Interrupt
IVG7
1
DMAR1 Block Interrupt
IVG7
1
DMAR0 Overflow Error
IVG7
1
DMAR1 Overflow Error
IVG7
1
CAN Error
IVG7
2
Ethernet Error (ADSP-BF536 and
ADSP-BF537 only)
IVG7
2
SPORT 0 Error
IVG7
2
SPORT 1 Error
IVG7
2
PPI Error
IVG7
2
SPI Error
IVG7
2
UART0 Error
IVG7
2
UART1 Error
IVG7
2
Real-Time Clock
IVG8
3
DMA Channel 0 (PPI)
IVG8
4
DMA Channel 3 (SPORT 0 Rx)
IVG9
5
DMA Channel 4 (SPORT 0 Tx)
IVG9
6
DMA Channel 5 (SPORT 1 Rx)
IVG9
7
DMA Channel 6 (SPORT 1 Tx)
IVG9
8
TWI
IVG10
9
DMA Channel 7 (SPI)
IVG10
10
DMA Channel 8 (UART0 Rx)
IVG10
11
DMA Channel 9 (UART0 Tx)
IVG10
12
DMA Channel 10 (UART1 Rx)
IVG10
13
DMA Channel 11 (UART1 Tx)
IVG10
14
CAN Rx
IVG11
15
CAN Tx
IVG11
16
DMA Channel 1 (Ethernet Rx,
ADSP-BF536 and ADSP-BF537 only)
IVG11
17
Port H Interrupt A
IVG11
17
DMA Channel 2 (Ethernet Tx,
ADSP-BF536 and ADSP-BF537 only)
IVG11
18
Port H Interrupt B
IVG11
18
Timer 0
IVG12
19
Timer 1
IVG12
20
Timer 2
IVG12
21
Timer 3
IVG12
22
Timer 4
IVG12
23
Timer 5
IVG12
24
Timer 6
IVG12
25
Timer 7
IVG12
26
Port F, G Interrupt A
IVG12
27
Port G Interrupt B
IVG12
28
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