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參數(shù)資料
| 型號： | ADW54012Z-0REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CROSSPOINT SWITCH 8X8 32LFCSP |
| 標準包裝： | 1,500 |
| 功能： | 交叉點開關 |
| 電路： | 1 x 8:8 |
| 導通狀態(tài)電阻： | 35 歐姆 |
| 電壓電源： | 單/雙電源 |
| 電壓 - 電源，單路/雙路(±)： | 12 V，±5 V |
| 電流 - 電源： | 50nA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
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ADG2188
Rev. 0 | Page 20 of 28
WRITING TO THE ADG2188
INPUT SHIFT REGISTER
The input shift register is 24 bits wide. A 3-byte write is necessary when writing to this register and is done under the control of the serial
clock input, SCL. The contents of the three bytes of the input shift register are shown in Figure 33 and described in Table 6.
X
XXXX
XX
LDSW
DB0 (LSB)
DB7 (MSB)
DATA BITS
DATA AX3 AX2 AX1 AX0 AY2 AY1 AY0
DB8 (LSB)
DB15 (MSB)
DATA BITS
1
11
0
A2
A1
A0
R/W
DB16 (LSB)
DEVICE ADDRESS
DB23 (MSB)
0
58
97
-004
Figure 33. Data-Words
Table 6. Input Shift Register Bit Function Descriptions
Bit
Mnemonic
Description
DB23 to DB17
1110xxx
The MSBs of the ADG2188 are set to 1110. The LSBs of the address byte are set by the
state of the three address pins, Pin A0, Pin A1, and Pin A2.
DB16
R/W
Controls whether the ADG2188 slave device is read from or written to.
If R/W = 1, the ADG2188 is being read from.
If R/W = 0, the ADG2188 is being written to.
DB15
Data
Controls whether the switch is to be open (off ) or closed (on).
If Data = 0, the switch is open/off.
If Data = 1, the switch is closed/on.
DB14 to DB11
AX3 to AX0
Controls I/Os X0 to X7. See Table 7 for the decode truth table.
DB10 to DB8
AY2 to AY0
Controls I/Os Y0 to Y7. See Table 7 for the decode truth table.
DB7 to DB1
X
Don’t care.
DB0
LDSW
This bit is useful when a number of switches need to be updated simultaneously.
If LDSW = 1, the switch position changes after the new word is read in.
If LDSW = 0, the input data is latched, but the switch position is not changed.
As shown in Table 6, Bit DB11 to Bit DB14 control the X input/output lines, while Bit DB8 to Bit DB10 control the Y input/output lines.
Table 7 shows the truth table for these bits. Note that the full coding sequence is written out for Channel Y0, and Channel Y1 to Channel Y7
follow a similar pattern. Note also that the RESET pin must be high when writing to the device.
Table 7. Address Decode Truth Table
DB15
DATA
DB14
AX3
DB13
AX2
DB12
AX1
DB11
AX0
DB10
AY2
DB9
AY1
DB8
AY0
Switch Configuration
1
0
X0 to Y0 (on)
0
X0 to Y0 (off )
1
0
1
0
X1 to Y0 (on)
0
1
0
X1 to Y0 (off )
1
0
1
0
X2 to Y0 (on)
0
1
0
X2 to Y0 (off )
1
0
1
0
X3 to Y0 (on)
0
1
0
X3 to Y0 (off )
1
0
1
0
X4 to Y0 (on)
0
1
0
X4 to Y0 (off )
1
0
1
0
1
0
X5 to Y0 (on)
0
1
0
1
0
X5 to Y0 (off )
X
0
1
0
Reserved
X
0
1
0
Reserved
1
0
X6 to Y0 (on)
0
1
0
X6 to Y0 (off )
1
0
1
0
X7 to Y0 (on)
0
1
0
1
0
X7 to Y0 (off )
X
1
0
1
0
Reserved
X
1
0
1
0
Reserved
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