- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374048 > ADV7391 (Analog Devices, Inc.) Low Power, Chip Scale 10-Bit SD/HD Video Encoder PDF資料下載
參數(shù)資料
| 型號： | ADV7391 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| 中文描述： | 低功耗，芯片尺寸10位標清/高清視頻編碼器 |
| 文件頁數(shù)： | 60/96頁 |
| 文件大小： | 1209K |
| 代理商： | ADV7391 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁當前第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁
ADV7390/ADV7391/ADV7392/ADV7393
EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL
For timing synchronization purposes, the ADV739x is able to accept either EAV/SAV time codes embedded in the input pixel data or
external synchronization signals provided on the HSYNC and VSYNC pins (see Table 48). It is also possible to output synchronization
signals on the HSYNC and VSYNC pins (see Table 49 to Table 51).
Rev. 0 | Page 61 of 96
Table 48. Timing Synchronization Signal Input Options
Signal
Pin
SD HSYNC In
HSYNC
SD VSYNC/FIELD In
VSYNC
ED/HD HSYNC In
HSYNC
ED/HD VSYNC/FIELD In
VSYNC
Condition
SD Slave Timing Mode 1, Mode 2, or Mode 3 Selected (Subaddress 0x8A[2:0]).
1
SD Slave Timing Mode 1, Mode 2, or Mode 3 Selected (Subaddress 0x8A[2:0]).
1
ED/HD Timing Synchronization Inputs Enabled (Subaddress 0x30, Bit 2 = 0).
ED/HD Timing Synchronization Inputs Enabled (Subaddress 0x30, Bit 2 = 0).
1
SD and ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02[7:6] = 00).
Table 49. Timing Synchronization Signal Output Options
Signal
Pin
SD HSYNC Out
HSYNC
SD VSYNC/FIELD Out
VSYNC
ED/HD HSYNC Out
HSYNC
ED/HD VSYNC/FIELD Out
VSYNC
Condition
SD Timing Synchronization Outputs enabled (Subaddress 0x02, Bit 6 = 1).
1
SD Timing Synchronization Outputs enabled (Subaddress 0x02, Bit 6 = 1).
1
ED/HD Timing Synchronization Outputs enabled (Subaddress 0x02, Bit 7 = 1).
2
ED/HD Timing Synchronization Outputs enabled (Subaddress 0x02, Bit 7 = 1).
2
1
ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02, Bit 7 = 0).
2
ED/HD timing synchronization inputs must also be disabled, that is, embedded EAV/SAV timing codes must be enabled (Subaddress 0x30, Bit 2 = 1).
Table 50. HSYNC Output Control
1
ED/HD Input Sync
Format (0x30, Bit 2)
x
x
ED/HD HSYNC
Control
(0x34, Bit 1)
x
x
ED/HD Sync
Output Enable
(0x02, Bit 7)
0
0
SD Sync
Output Enable
(0x02, Bit 6)
0
1
Signal on HSYNC Pin
Tristate.
Pipelined SD HSYNC.
Duration
–
See
Error! Reference
source not found.
.
As per HSYNC timing.
Same as line blanking
interval.
Same as embedded
HSYNC.
0
1
0
0
1
1
x
x
Pipelined ED/HD HSYNC.
Pipelined ED/HD HSYNC based on
AV Code H bit.
Pipelined ED/HD HSYNC based on
horizontal counter.
x
1
1
x
1
In all ED/HD standards where there is a HSYNC output, the start of the HSYNC pulse is aligned with the falling edge of the embedded HSYNC in the output video.
Table 51. VSYNC Output Control
1
ED/HD Input
Sync Format
(0x30, Bit 2)
(0x34, Bit 2)
x
x
x
x
ED/HD VSYNC
Control
ED/HD Sync
Output Enable
(0x02, Bit 7)
0
0
SD Sync
Output Enable
(0x02, Bit 6)
0
1
Video Standard
x
Interlaced
Signal on VSYNC Pin
Tristate.
Pipelined SD VSYNC/Field.
Duration
–
See
Error!
Reference source
not found.
.
As per VSYNC or
Field signal timing.
Field.
0
0
1
x
x
Pipelined ED/HD VSYNC
or field signal.
Pipelined Field signal
based on AV Code F bit.
Pipelined VSYNC based on
AV Code V bit.
Pipelined ED/HD VSYNC
based on vertical counter.
Pipelined ED/HD VSYNC
based on vertical counter.
1
0
1
x
All HD interlaced
standards
All ED/HD progressive
standards
All ED/HD standards
except 525p
525p
1
0
1
x
Vertical blanking
interval.
Aligned with
serration lines.
Vertical blanking
interval.
x
1
1
x
x
1
1
x
1
In all ED/HD standards where there is a VSYNC output, the start of the VSYNC pulse is aligned with the falling edge of the embedded VSYNC in the output video.
相關PDF資料 |
PDF描述 |
|---|---|
| ADV7391BCPZ | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7391BCPZ-REEL | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7391EBZ | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7392 | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7392BCPZ | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7391BCBZ-A-RL | 功能描述:視頻 IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| ADV7391BCPZ | 功能描述:IC ENCODER VIDEO W/DAC 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7391BCPZ-REEL | 功能描述:IC VIDEO ENCODER SD/HD 32-LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7391EBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7391WBCPZ | 制造商:Analog Devices 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。