參數(shù)資料
型號： ADV7194
廠商： Analog Devices, Inc.
英文描述： Professional Extended-10⑩ Video Encoder with 54 MHz Oversampling
中文描述： 專業(yè)擴展- 10⑩視頻編碼器，54兆赫采樣
文件頁數(shù)： 41/69頁
文件大小： 647K
代理商： ADV7194
ADV7194
–41–
REV. 0
SHARPNESS RESPONSE REGISTER (PR)
(Address (SR5–SR0) = 22H)
The sharpness response register is an 8-bit-wide register. The
four MSBs are set to 0. The four LSBs are written to in order to
select a desired
fi
lter response. Figure 82 shows the operation
under control of this register.
PR BIT DESCRIPTION
Sharpness Response Select Value (PR3–PR0)
These four bits are used to select the desired luma
fi
lter response. The
option of twelve responses is given supporting a gain boost/
attenuation in the range
–
4 dB to +4 dB. The value 12 (1100)
written to these four bits corresponds to a boost of +4 dB while
the value 0 (0000) corresponds to
–
4 dB. For normal operation
these four bits are set to 6 (0110). Note: Luma Filter Select has
to be set to Extended Mode and Sharpness Filter Control has to
be enabled for settings in the Sharpness Response Register to
take effect (MR02
–
04 = 100; MR74 = 1).
Reserved (PR4–PR7)
A Logic 0 must be written to these bits.
PR3
–
PR0
SHARPNESS
RESPONSE SELECT
ZERO MUST BE
WRITTEN TO
THESE BITS
PR7
–
PR4
PR7
PR6
PR5
PR4
PR3
PR2
PR1
PR0
Figure 82. Sharpness Response Register
DNR REGISTERS 2–0
(DNR 2–DNR 0)
(Address (SR5–SR0) = 23H–25H)
The Digital Noise Reduction Registers are three 8-bit-wide
register. They are used to control the DNR processing. See
also the Functional Description section.
Coring Gain Border (DNR00–DNR03)
These four bits are assigned to the gain factor applied to border
areas.
In DNR Mode the range of gain values is 0
–
1, in increments of
1/8. This factor is applied to the DNR
fi
lter output which lies
below the set threshold range. The result is then subtracted
from the original signal.
In DNR Sharpness Mode the range of gain values is 0
–
0.5, in
increments of 1/16. This factor is applied to the DNR
fi
lter out-
put which lies above the threshold range.
The result is added to the original signal.
Coring Gain Data (DNR04–DNR07)
These four bits are assigned to the gain factor applied to the
luma data inside the MPEG pixel block.
In DNR Mode the range of gain values is 0
–
1, in increments of
1/8. This factor is applied to the DNR
fi
lter output which lies
below the set threshold range. The result is then subtracted
from the original signal.
In DNR Sharpness Mode the range of gain values is 0
–
0.5, in
increments of 1/16. This factor is applied to the DNR
fi
lter out-
put which lies above the threshold range. The result is added to
the original signal.
Figures 79 and 80 show the various operations under the control
of DNR Register 0.
DNR07
DNR06
DNR05
DNR04
DNR03
DNR02
DNR01
DNR00
CORING GAIN DATA
DNR DNR DNR DNR
07 06 05 04
0 0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
+1/16
+2/16
+3/16
+4/16
+5/16
+6/16
+7/16
+8/16
CORING GAIN BORDER
DNR DNR DNR DNR
03 02 01 00
0 0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
+1/16
+2/16
+3/16
+4/16
+5/16
+6/16
+7/16
+8/16
Figure 83. DNR Register 0 in Sharpness Mode
CORING GAIN DATA
DNR DNR DNR DNR
07 06 05 04
0 0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
–
1/8
–
2/8
–
3/8
–
4/8
–
5/8
–
6/8
–
7/8
–
1
CORING GAIN BORDER
DNR DNR DNR DNR
03 02 01 00
0 0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
–
1/8
–
2/8
–
3/8
–
4/8
–
5/8
–
6/8
–
7/8
–
1
DNR07
DNR06
DNR05
DNR04
DNR03
DNR02
DNR01
DNR00
Figure 84. DNR Register 0 in DNR Mode
DNR1 BIT DESCRIPTION
DNR Threshold (DNR10–DNR15)
These six bits are used to de
fi
ne the threshold value in the range
of 0 to 63. The range is an absolute value.
Border Area (DNR16)
In setting DNR16 to a Logic 1 the block transition area can be
de
fi
ned to consist of four pixels. If this bit is set to a Logic 0 the
border transition area consists of two pixels, where one pixel
refers to two clock cycles at 27 MHz.
Block Size Control (DNR17)
This bit is used to select the size of the data blocks to be pro-
cessed (see Figure 85). Setting the block size control function to
a Logic 1 de
fi
nes a 16
×
16 pixel data block, a Logic 0 de
fi
nes an
8
×
8 pixel data block, where one pixel refers to two clock cycles
at 27 MHz.
720 485 PIXELS
(NTSC)
2 PIXEL
PIX8 8
PIX8 8
Figure 85. MPEG Block Diagram
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7194KST 制造商:Analog Devices 功能描述:Video Encoder 6DAC 10-Bit 80-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:PROFESSIONAL/HDTV NTSC/PAL ENCODER I.C. - Bulk 制造商:Analog Devices 功能描述:IC VIDEO ENCODER
ADV7194KSTZ 功能描述:IC ENCODER VIDEO EXT-10 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799
ADV7194KSTZ 制造商:Analog Devices 功能描述:TV / Video IC
ADV7195 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input
ADV7195KS 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:MULTI-FORMAT VID+PROGSCAN/HDTV ENCODERIC - Bulk
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