參數(shù)資料
型號: ADV7192KST
廠商: ANALOG DEVICES INC
元件分類: 顏色信號轉(zhuǎn)換
英文描述: Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs
中文描述: COLOR SIGNAL ENCODER, PQFP80
封裝: LQFP-80
文件頁數(shù): 10/69頁
文件大?。?/td> 664K
代理商: ADV7192KST
ADV7192
10
REV. 0
PIN FUNCTION DESCRIPTIONS
Pin
No.
Input/
Output
Mnemonic
Function
1, 2
3–10
NC
P0–P7
No Connect.
8-Bit 4:2:2 Multiplexed YCrCb Pixel Port. The LSB of the input data is set up on Pin P0
(Pin Number 3).
16-Bit 4:2:2 Multiplexed YCrCb Pixel Port (Bits 8–15). 1
×
10-bit progressive scan input for
Ydata (Bits 0–7).
1
×
10-bit progressive scan input is Ydata (Bits 8 and 9).
Digital Power Supply (3.3 V to 5 V).
Digital Ground.
I
11–18
Y0/P8–Y7/P15
I
19, 20
21, 34, 68, 79
22, 33, 43, 69,
80
23
Y8–Y9
V
DD
DGND
P
G
HSYNC
I/O
HSYNC
(Modes 1, 2, and 3) Control Signal. This pin may be configured to be an output
(Master Mode) or an input (Slave Mode) and accept Sync Signals.
VSYNC
Control Signal. This pin may be configured as an output (Master Mode) or as an
input (Slave Mode) and accept
VSYNC
as a Control Signal.
Video Blanking Control Signal. This signal is optional. For further information see
Vertical Blanking and Data Insertion Blanking Input section.
1
×
10-Bit Progressive Scan Input Port for Cb data.
Teletext Data Request Output Signal, used to control teletext data transfer.
Analog Ground.
TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation.
Alternatively, a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel
operation.
Clock Output pin.
Analog Power Supply (3.3 V to 5 V).
MPU Port Serial Interface Clock Input.
MPU Port Serial Data Input/Output.
Multifunctional Input: Real Time Control (RTC) input, Timing Reset input, Subcarrier
Reset input.
TTL Address Input. This signal sets up the LSB of the MPU address.
A 1200
resistor connected from this pin to GND is used to control full-scale amplitudes
of the Video Signals from the DAC D, E, F.
Compensation Pin for DACs D, E, and F. Connect a 0.1
μ
F Capacitor from COMP2
to V
AA
.
S-Video C/Pr/V/RED Analog Output. This DAC is capable of providing 4.33 mA output.
S-Video Y/Pb/U/BLUE Analog Output. This DAC is capable of providing 4.33 mA output.
Composite/Y (progressive scan)/Y/Green Analog Output. This DAC is capable of providing
4.33 mA output.
S-Video C/Pr/V/RED Analog Output. This DAC is capable of providing 4.33 mA output.
S-Video Y/Pb/U/BLUE Analog Output. This DAC is capable of providing 4.33 mA output.
Composite/Y(progressive scan)/Y/Green Analog Output. This DAC is capable of providing
4.33 mA output.
Compensation Pin for DACs A, B, and C. Connect a 0.1
μ
F Capacitor from COMP1 to V
AA
.
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). An external
V
REF
cannot be used in 4
×
Oversampling Mode.
A 1200
resistor connected from this pin to GND is used to control full-scale amplitudes
of the Video Signals from the DAC A, B, C.
Input signal to select PAL or NTSC mode of operation, pin set to Logic 1 selects PAL.
The input resets the on-chip timing generator and sets the ADV7192 into default mode.
See Appendix 8 for Default Register settings.
Dual function
CSO
or
HSO
Output Sync Signal at TTL Level.
Multifunctional Pin.
VSO
Output Sync Signal at TTL level. Teletext Data Input pin.
CLAMP TTL output signals can be used to drive external circuitry to enable clamping
of all video signals.
1
×
10-Bit progressive scan input port for Cr data.
24
VSYNC
I/O
25
BLANK
I/O
26–31, 75–78
32
35, 49, 52
36
Cb4–Cb9, Cb0–Cb3
TTXREQ
AGND
CLKIN
I
O
G
I
37
38, 48, 53
39
40
41
CLKOUT
V
AA
SCL
SDA
SCRESET/
RTC/TR
ALSB
R
SET2
O
P
I
I/O
I
42
44
I
I
45
COMP 2
O
46
47
50
DAC F
DAC E
DAC D
O
O
O
51
54
55
DAC C
DAC B
DAC A
O
O
O
56
57
COMP 1
V
REF
O
I/O
58
R
SET1
I
59
60
PAL_NTSC
RESET
I
I
61
62
CSO_HSO
VSO
/TTX/CLAMP
O
I/O
63–67, 70–74
Cr0–Cr4, Cr5–Cr9
I
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