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參數(shù)資料
| 型號： | ADV7183BKSTZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | Multiformat SDTV Video Decoder |
| 中文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | LEAD FREE, MS-026-BEC, LQFP-80 |
| 文件頁數(shù)： | 60/100頁 |
| 文件大?。?/td> | 844K |
| 代理商： | ADV7183BKSTZ |
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ADV7183B
MPU PORT DESCRIPTION
The ADV7183B supports a 2-wire (I
2
C-compatible) serial inter-
face. Two inputs, serial data (SDA) and serial clock (SCLK),
carry information between the ADV7183B and the system I
2
C
master controller. Each slave device is recognized by a unique
address. The ADV7183B’s I
2
C port allows the user to set up and
configure the decoder and to read back captured VBI data. The
ADV7183B has two possible slave addresses for both read and
write operations, depending on the logic level on the ALSB pin.
These four unique addresses are shown in
262H
Table 81. The
ADV7183B’s ALSB pin controls Bit 1 of the slave address. By
altering the ALSB, it is possible to control two ADV7183Bs in
an application without having a conflict with the same slave
address. The LSB (Bit 0) sets either a read or write operation.
Logic 1 corresponds to a read operation; Logic 0 corresponds to
a write operation.
Table 81. I
2
C Address for the ADV7183B
ALSB
R/W
Slave Address
0
0
0x40
0
1
0x41
1
0
0x42
1
1
0x43
To control the device on the bus, a specific protocol must be
followed. First, the master initiates a data transfer by
establishing a start condition, which is defined by a high-to-low
transition on SDA while SCLK remains high. This indicates that
an address/data stream will follow. All peripherals respond to
the start condition and shift the next eight bits (7-bit address +
R/W bit). The bits are transferred from MSB down to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse; this is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDA and SCLK lines,
waiting for the start condition and the correct transmitted
Rev. B | Page 60 of 100
address. The R/W bit determines the direction of the data.
Logic 0 on the LSB of the first byte means the master writes
information to the peripheral. Logic 1 on the LSB of the first
byte means the master reads information from the peripheral.
The ADV7183B acts as a standard slave device on the bus. The
data on the SDA pin is eight bits long, supporting the 7-bit
addresses and the R/W bit. The ADV7183B has 249 subad-
dresses to enable access to the internal registers. It therefore
interprets the first byte as the device address and the second
byte as the starting subaddress. The subaddresses auto-increment,
which allows data to be written to or read from the starting sub-
address. A data transfer is always terminated by a stop condition.
The user can also access any unique subaddress register on a
one-by-one basis without updating all the registers.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCLK high period,
the user should only issue one start condition, one stop condition,
or a single stop condition followed by a single start condition. If
an invalid subaddress is issued by the user, the ADV7183B does
not issue an acknowledge and returns to the idle condition.
If the user exceeds the highest subaddress in auto-increment
mode, the following occurs:
In read mode, the highest subaddress register contents
continue to be output until the master device issues a
no-acknowledge. This indicates the end of a read. A no
acknowledge condition is where the SDA line is not pulled
low on the ninth pulse.
In write mode, the data for the invalid byte is not loaded
into any subaddress register, a no acknowledge is issued by
the ADV7183B, and the part returns to the idle condition.
SDATA
SCLOCK
START ADDR
ACK
ACK
DATA
ACK
STOP
SUBADDRESS
1–7
1–7
8
9
8
9
1–7
8
9
S
P
R/W
0
Figure 39. Bus Data Transfer
S
WRITE
SEQUENCE
SLAVE ADDR
A(S)
SUB ADDR
A(S)
DATA
A(S)
DATA
A(S)
P
S
READ
SEQUENCE
SLAVE ADDR
SLAVE ADDR
A(S)
SUB ADDR
A(S) S
A(S)
DATA
A(M)
DATA
A(M) P
S = START BIT
P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
LSB = 1
LSB = 0
0
Figure 40. Read and Write Sequence
相關PDF資料 |
PDF描述 |
|---|---|
| ADV7183KST | Advanced Video Decoder with 10-Bit ADC and Component Input Support |
| AD7183 | Advanced Video Decoder with 10-Bit ADC and Component Input Support |
| ADV7185 | Professional NTSC/PAL Video Decoder with 10-Bit CCIR656 Output |
| ADV7185KST | Professional NTSC/PAL Video Decoder with 10-Bit CCIR656 Output |
| ADV7190KST | Video Encoder with Six 10-Bit DACs and Video Encoder with Six DAC Outputs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7183KST | 制造商:Analog Devices 功能描述:Video Decoder 2ADC 10-Bit 80-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:VIDEO DECODER I.C. - Bulk |
| ADV7184 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder with Fast Switch Overlay Support |
| ADV7184BSTZ | 功能描述:IC DECODER VID SDTV MULTI 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7185 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Professional NTSC/PAL Video Decoder with 10-Bit CCIR656 Output |
| ADV7185KST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Professional NTSC/PAL Video Decoder with 10-Bit CCIR656 Output |
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