tPD is th" />
參數(shù)資料
型號： ADV7179BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 39/52頁
文件大?。?/td> 0K
描述： IC ENCODER VID NTSC/PAL 40LFCSP
產(chǎn)品培訓(xùn)模塊： Interfacing AV Converters to Blackfin Processors
標(biāo)準(zhǔn)包裝： 1
類型： 視頻編碼器
應(yīng)用： 數(shù)碼相機(jī)，手機(jī)，便攜式視頻
電壓 - 電源，模擬： 2.8 V，3.3 V
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP-VQ（6x6）
包裝： 托盤
產(chǎn)品目錄頁面： 786 (CN2011-ZH PDF)
ADV7174/ADV7179
Rev. B | Page 44 of 52
APPENDIX 5—TELETEXT
TELETEXT INSERTION
tPD is the time needed by the ADV7174/ADV7179 to interpolate
input data on TTX and insert it onto the CVBS or Y outputs,
such that it appears tSYNTTXOUT = 10.2 μs after the leading edge of
the horizontal signal. Time TTXDEL is the pipeline delay time by
the source that is gated by the TTXREQ signal in order to
deliver TTX data.
With the programmability offered with the TTXREQ signal on
the rising/falling edges, the TTX data is always inserted at the
correct position of 10.2 μs after the leading edge of horizontal
sync pulse, thus enabling a source interface with variable pipe-
line delays.
The width of the TTXREQ signal must always be maintained to
allow the insertion of 360 (to comply with the Teletext standard
PAL-WST) Teletext bits at a text data rate of 6.9375 Mbits/s.
This is achieved by setting TC03–TC00 to 0. The insertion
window is not open if the Teletext enable bit (MR35) is set to 0.
TELETEXT PROTOCOL
The relationship between the TTX bit clock (6.9375 MHz) and
the system clock (27 MHz) for 50 Hz is
() 027777
.
1
10
75
.
6
10
9375
.
6
75
.
6
4
6
27
=
×
=
MHz
Thus, 37 TTX bits correspond to 144 clocks (27 MHz) and each
bit has a width of almost four clock cycles. The ADV7174/
ADV7179 uses an internal sequencer and variable phase inter-
polation filter to minimize the phase jitter and thus generate a
band-limited signal that can be output on the CVBS and Y
outputs.
At the TTX input, the bit duration scheme repeats after every
37 TTX bits or 144 clock cycles. The protocol requires that TTX
Bits 10, 19, 28, and 37 are carried by three clock cycles and all
other bits by four clock cycles. After 37 TTX bits, the next bits
with three clock cycles are 47, 56, 65, and 74. This scheme holds
for all following cycles of 37 TTX bits until all 360 TTX bits are
completed. All Teletext lines are implemented in the same way.
Individual control of Teletext lines is controlled by Teletext
setup registers.
ADDRESS AND DATA
RUN-IN CLOCK
TELETEXT VBI LINE
45 BYTES (360 BITS) – PAL
02980-A
-058
Figure 59. Teletext VBI Line
PROGRAMMABLE PULSE EDGES
tPD
CVBS/Y
HSYNC
TTXREQ
TTXDATA
tSYNTTXOUT = 10.2μs
tPD = PIPELINE DELAY THROUGH ADV7174/ADV7179
TTXDEL = TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES])
tSYNTTXOUT
10.2
μs
TTXDEL
TTXST
02980-A
-059
Figure 60. Teletext Functionality
相關(guān)PDF資料
PDF描述
VE-231-IY-F3 CONVERTER MOD DC/DC 12V 50W
VE-B7L-IW-B1 CONVERTER MOD DC/DC 28V 100W
CS4954-CQZ IC VIDEO ENCODER NTSC/PAL 48TQFP
VE-230-IY-F4 CONVERTER MOD DC/DC 5V 50W
VE-B7K-IX-B1 CONVERTER MOD DC/DC 40V 75W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7179BCPZ2 制造商:AD 制造商全稱:Analog Devices 功能描述:Chip Scale PAL/NTSC Video Encoder with Advanced Power Management
ADV7179BCPZ-REEL 制造商:Analog Devices 功能描述:Video Encoder 3DAC 10-Bit 40-Pin LFCSP EP T/R
ADV7179BCPZ-REEL2 制造商:AD 制造商全稱:Analog Devices 功能描述:Chip Scale PAL/NTSC Video Encoder with Advanced Power Management
ADV7179KCP 制造商:Analog Devices 功能描述:Video Encoder 3DAC 10-Bit 40-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:CHIP SCALE NTSC/PAL VID ENCODER APM I.C. - Bulk 制造商:Analog Devices 功能描述:IC VIDEO ENCODER
ADV7179KCP1 制造商:AD 制造商全稱:Analog Devices 功能描述:Chip Scale PAL/NTSC Video Encoder with Advanced Power Management
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*