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參數(shù)資料
| 型號： | ADV7179 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Chip Scale PAL/NTSC Video Encoder with Advanced Power Management |
| 中文描述： | 芯片級PAL / NTSC制式視頻編碼器與高級電源管理 |
| 文件頁數(shù)： | 10/52頁 |
| 文件大?。?/td> | 488K |
| 代理商： | ADV7179 |
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ADV7174/ADV7179
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. A | Page 10 of 52
11
12
13
14
15
16
17
18
19
20
3
4
5
6
7
1
2
10
8
9
37
36
35
38
39
40
33
32
31
34
26
27
28
29
24
25
22
23
21
30
V
REF
DAC A
DAC B
V
AA
GND
V
AA
DAC C
B
G
G
H
F
A
CLOCK
V
AA
P5
P6
P7
GND
GND
GND
GND
V
AA
COMP
SDATA
SCLOCK
G
V
A
G
R
G
P
P
P
P
P
T
T
R
S
S
R
PIN 1
ADV7174/ADV7179
LFCSP
TOP VIEW
(Not to Scale)
0
Figure 5. Pin Configurations
Table 6. Pin Function Descriptions
Input/
Output
P7–P0
I
CLOCK
I
Mnemonic
Function
8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0). P0 is the LSB.
TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation. Alternatively, a 24.5454 MHz
(NTSC) or 29.5 MHz (PAL) can be used for square pixel operation.
HSYNC (Modes 1 and 2) Control Signal. This pin may be configured to output (master mode) or accept (slave
mode) sync signals.
Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This pin may be configured to output
(master mode) or accept (slave mode) these control signals.
Video Blanking Control Signal. The pixel inputs are ignored when this is Logic 0. This signal is optional.
This pin can be configured as an input by setting MR22 and MR21 of Mode Register 2. It can be configured as a
subcarrier reset pin, in which case a low-to-high transition on this pin resets the subcarrier to Field 0.
Alternatively, it can be configured as a real-time control (RTC) input.
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
A 150 resistor connected from this pin to GND is used to control full-scale amplitudes of the video signals.
Compensation Pin. Connect a 0.1 μF capacitor from COMP to V
AA
. For optimum dynamic performance in low
power mode, the value of the COMP capacitor can be lowered to as low as 2.2 nF.
DAC Output (see Table 13)
DAC Output (see Table 13).
DAC Output (see Table 13).
MPU Port Serial Interface Clock Input.
MPU Port Serial Data Input/Output.
TTL Address Input. This signal sets up the LSB of the MPU address.
This input resets the on-chip timing generator and sets the ADV7174/ADV7179 into default mode. This is NTSC
operation, Timing Slave Mode 0, 8-bit operation, 2× composite out signals. DACs A, B, and C are enabled.
Teletext Data.
Teletext Data Request Signal/Defaults to GND when Teletext Not Selected.
Power Supply (2.8 V or 3.3 V).
Ground Pin.
HSYNC
I/O
FIELD/VSYNC I/O
BLANK
SCRESET/RTC I
I/O
V
REF
R
SET
COMP
I/O
I
O
DAC A
DAC B
DAC C
SCLOCK
SDATA
ALSB
RESET
O
O
O
I
I/O
I
I
TTX
TTXREQ
V
AA
GND
I
O
P
G
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| ADV7179BCP | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 10-Bit 40-Pin LFCSP EP 制造商:Analog Devices 功能描述:IC VIDEO ENCODER |
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| ADV7179BCP-REEL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Chip Scale PAL/NTSC Video Encoder with Advanced Power Management |
| ADV7179BCPZ | 功能描述:IC ENCODER VID NTSC/PAL 40LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
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