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參數(shù)資料
| 型號： | ADV7178KS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Integrated Digital CCIR-601 to PAL/NTSC Video Encoder |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP44 |
| 封裝： | PLASTIC, MO-112-AA-1, MQFP-44 |
| 文件頁數(shù)： | 26/38頁 |
| 文件大?。?/td> | 280K |
| 代理商： | ADV7178KS |
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ADV7177/ADV7178
–26–
REV. 0
TIMING REGISTER 1 (TR17–TR10)
(Address [SR4–SR0] = 0CH)
Timing Register 1 is an 8-bit-wide register.
Figure 38 shows the various operations under the control of
Timing Register 1. This register can be read from as well as
written to. This register can be used to adjust the width and
position of the master mode timing signals.
TR1 BIT DESCRIPTION
HSYNC
Width (TR11–TR10)
These bits adjust the
HSYNC
pulsewidth.
HSYNC
to
VSYNC
/FIELD Delay Control (TR13–TR12)
These bits adjust the position of the
HSYNC
output relative to
the FIELD/
VSYNC
output.
HSYNC
to FIELD Delay Control (TR15–TR14)
When the ADV7177/ADV7178 is in Timing Mode 1, these bits
adjust the position of the
HSYNC
output relative to the FIELD
output rising edge.
VSYNC
Width (TR15–TR14)
When the ADV7177/ADV7178 is in Timing Mode 2, these bits
adjust the
VSYNC
pulsewidth.
HSYNC
to Pixel Data Adjust (TR17–TR16)
This enables the
HSYNC
to be adjusted with respect to the
pixel data. This allows the Cr and Cb components to be
swapped. This adjustment is available in both master and slave
timing modes.
MODE REGISTER 2 MR2 (MR27–MR20)
(Address [SR4-SR0] = 0DH)
Mode Register 2 is an 8-bit-wide register.
Figure 39 shows the various operations under the control of Mode
Register 2. This register can be read from as well as written to.
MR2 BIT DESCRIPTION
Square Pixel Mode Control (MR20)
This bit is used to set up square pixel mode. This is available in
slave mode only. For NTSC, a 24.54 MHz clock must be sup-
plied. For PAL, a 29.5 MHz clock must be supplied.
Active Video Line Control (MR23)
This bit switches between two active video line durations. A
zero selects ITU-R BT.470 (720 pixels PAL/NTSC) and a one
selects ITU-R/SMPTE “analog” standard for active video dura-
tion (710 pixels NTSC 702 pixels PAL).
Chrominance Control (MR24)
This bit enables the color information to be switched on and off
the video output.
Burst Control (MR25)
This bit enables the burst information to be switched on and off
the video output.
RGB/YUV Control (MR26)
This bit enables the output from the RGB DACs to be set to
YUV output video standard. Bit MR06 of Mode Register 0
must be set to Logic Level “1” before MR26 is set.
Table II. DAC Output Configuration Matrix
MR06
MR26
DAC A
DAC B
DAC C
0
0
1
1
0
1
0
1
CVBS
CVBS
B
U
Y
Y
S
Y
C
C
R
V
CVBS: Composite Video Baseband Signal
Y:
Luminance Component Signal (For YUV or Y/C Mode)
C:
Chrominance Signal (For Y/C Mode)
U:
Chrominance Component Signal (For YUV Mode)
V:
Chrominance Component Signal (For YUV Mode)
R:
RED Component Video (For RGB Mode)
G:
GREEN Component Video (For RGB Mode)
B:
BLUE Component Video (For RGB Mode)
Low Power Control (MR27)
This bit enables the lower power mode of the ADV7177/
ADV7178. This will reduce DAC current by 50%.
MR21
MR27
MR22
MR23
MR26
MR25
MR24
MR20
CHROMINANCE
CONTROL
MR24
0
1
ENABLE COLOR
DISABLE COLOR
RGB/YUV
CONTROL
MR26
0
1
RGB OUTPUT
YUV OUTPUT
SQUARE PIXEL
CONTROL
MR20
0
1
DISABLE
ENABLE
BURST
CONTROL
0
1
ENABLE BURST
DISABLE BURST
MR25
CCIR624/CCIR601
CONTROL
MR23
0 CCIR624 OUTPUT
1 CCIR601 OUTPUT
MR22–MR21
(00)
ZERO SHOULD
BE WRITTEN TO
THESE BITS
LOW POWER
MODE
MR27
0
1
DISABLE
ENABLE
Figure 39. Mode Register 2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7178KS-REEL | 制造商:Analog Devices 功能描述: |
| ADV7179 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Chip Scale PAL/NTSC Video Encoder with Advanced Power Management |
| ADV7179BCP | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 10-Bit 40-Pin LFCSP EP 制造商:Analog Devices 功能描述:IC VIDEO ENCODER |
| ADV7179BCP1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Chip Scale PAL/NTSC Video Encoder with Advanced Power Management |
| ADV7179BCP-REEL | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 10-Bit 40-Pin LFCSP EP T/R |
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