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ADV7175A/ADV7176A
–23–
REV. B
RE GIST E R ACCE SSE S
T he MPU can write to or read from all of the ADV7175A/
ADV7176A registers except the subaddress register, which is a
write-only register. T he subaddress register determines which
register the next read or write operation accesses. All communi-
cations with the part through the bus start with an access to the
subaddress register. A read/write operation is performed from/to
the target address, which then increments to the next address
until a stop command on the bus is performed.
RE GIST E R PROGRAMMING
T he following section describes each register, including subaddress
register, mode registers, subcarrier frequency registers, subcarrier
phase register, timing registers, closed captioning extended data
registers, closed captioning data registers and NT SC pedestal
control registers in terms of its configuration.
Subaddress Register (SR7–SR0)
T he communications register is an 8-bit write-only register.
After the part has been accessed over the bus, and a read/write
operation is selected, the subaddress is set up. T he subaddress
register determines to/from which register the operation takes
place.
Figure 31 shows the various operations under the control of
the subaddress register. Zero should always be written to
SR7–SR6.
Register Select (SR5–SR0)
T hese bits are set up to point to the required starting address.
MODE RE GIST E R 0 MR0 (MR07–MR00)
(Address [SR4–SR0] = 00H)
Figure 32 shows the various operations under the control of Mode
Register 0. T his register can be read from as well as written to.
MR0 BIT DE SCRIPT ION
E ncode Mode Control (MR01–MR00)
T hese bits are used to set up the encode mode. T he ADV7175A/
ADV7176A can be set up to output NT SC, PAL (B, D, G, H, I)
and PAL (M) standard video.
Pedestal Control (MR02)
T his bit specifies whether a pedestal is to be generated on
the NT SC composite video signal. T his bit is invalid if the
ADV7175A/ADV7176A is configured in PAL mode.
Luminance Filter Control (MR04–MR03)
T he luminance filters are divided into two sets (NT SC/PAL) of
four filters, low-pass A, low-pass B, notch and extended. When
PAL is selected, bits MR03 and MR04 select one of four PAL
luminance filters; likewise, when NT SC is selected, bits MR03
and MR04 select one of four NT SC luminance filters. T he fil-
ters are illustrated in Figures 4 to 12.
RGB Sync (MR05)
T his bit is used to set up the RGB outputs with the sync infor-
mation encoded on all RGB outputs.
Output Control (MR06)
T his bit specifies if the part is in composite video or RGB/YUV
mode. Please note that the main composite signal is still avail-
able in RGB/YUV mode.
MR01
MR00
MR07
MR02
MR04
MR03
MR05
MR06
OUTPUT VIDEO
STANDARD SELECTION
MR01 MR00
0
0
1
1
0
1
0
1
NTSC
PAL (B, D, G, H, I)
PAL (M)
RESERVED
MR07
(0)
ZERO SHOULD
BE WRITTEN TO
THIS BIT
OUTPUT SELECT
MR06
0
1
YC OUTPUT
RGB/YUV OUTPUT
FILTER SELECT
0
0
1
1
0
1
0
1
LOW PASS FILTER (A)
NOTCH FILTER
EXTENDED MODE
LOW PASS FILTER (B)
MR04 MR03
RGB SYNC
MR05
0
1
DISABLE
ENABLE
PEDESTAL CONTROL
MR02
0
1
PEDESTAL OFF
PEDESTAL ON
Figure 32. Mode Register 0 (MR0)
MR11
MR10
MR17
MR12
MR13
MR15
MR16
MR14
CLOSED CAPTIONING
FIELD SELECTION
MR12 MR11
0
0
1
1
0
1
0
1
NO DATA OUT
ODD FIELD ONLY
EVEN FIELD ONLY
DATA OUT
(BOTH FIELDS)
DAC A
CONTROL
0
1
NORMAL
POWER-DOWN
MR16
DAC D
CONTROL
MR14
0
1
DAC C
CONTROL
MR13
0
1
DAC B
CONTROL
MR15
0
1
INTERLACE
CONTROL
0
1
INTERLACED
NONINTERLACED
MR10
COLOR BAR
CONTROL
0
1
DISABLE
ENABLE
MR17
NORMAL
POWER-DOWN
NORMAL
POWER-DOWN
NORMAL
POWER-DOWN
Figure 33. Mode Register 1 (MR1)