參數(shù)資料
型號(hào)： ADV7175A
廠商： Analog Devices, Inc.
英文描述： High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder
中文描述： 高品質(zhì)，10位，數(shù)字無(wú)線電咨詢委員會(huì)，601到PAL / NTSC制式視頻編碼器
文件頁(yè)數(shù)： 14/52頁(yè)
文件大?。?/td> 629K
代理商： ADV7175A
ADV7175A/ADV7176A
–14–
REV. B
COMPOSITE
VIDEO
e.g., VCR
OR CABLE
M
U
X
HSYNC
FIELD/
VSYNC
ADV7175A/ADV7176A
CLOCK
GREEN/LUMA/Y
RED/CHROMA/V
BLUE/COMPOSITE/U
COMPOSITE
P7–P0
SCRESET/RTC
MPEG
DECODER
VIDEO
DECODER
(e.g., ADV7185)
H/LTRANSITION
COUNT START
LOW
128
RTC
TIME SLOT: 01
14
6768
NOT USED IN
ADV7175A/ADV7176A
19
VALID
SAMPLE
INVALID
SAMPLE
FSCPLL INCREMENT
1
8/LLC
5 BITS
RESERVED
SEQUENCE
BIT
RESET
BIT
3
RESERVED
4 BITS
RESERVED
21
0
13
14 BITS
RESERVED
NOTES:
1
F
SC
PLL INCREMENT IS 22 BITS LONG, VALUED LOADED INTO ADV7175A/ADV7176A FSC DDS REGISTER IS
F
PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUB CARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD
BE WRITTEN TO THE SUB CARRIER FREQUENCY REGISTERS OF THE ADV7175A/ADV7176A.
2
SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE.
3
RESET BIT
RESET ADV7175A/ADV7176A’s DDS.
0
Figure 13. RTC Timing and Connections
Vertical Blanking Data Insertion
It is possible to allow encoding of incoming YCbCr data on those lines of VBI that do not bear line sync or pre/post-equalization
pulses (see Figures 15 to 26). T his mode of operation is called “Partial Blanking” and is selected by setting MR31 to 1. It allows the
insertion of any VBI data (Opened VBI) into the encoded output waveform. T his data is present in digitized incoming YCbCr data
stream (e.g., WSS data, CGMS, VPS, etc.). Alternatively, the entire VBI may be blanked (no VBI data inserted) on these lines by
setting MR31 to 0.
T he complete VBI comprises of the following lines:
525/60 Systems, Lines 525 to 21 for Field 1 and Lines 262 to Line 284 for Field 2.
625/50 Systems, Lines 624 to Line 22 and Lines 311 to 335.
T he “Opened VBI” consists of:
525/60 Systems, Lines 10 to 21 for Field 1 and second half of Line 273 to Line 284 for Field 2.
625/50 Systems, Line 7 to Line 22 and Lines 319 to 335.
Mode 0 (CCIR-656): Slave Option
(T iming Register 0 T R0 = X X X X X 0 0 0)
T he ADV7175A/ADV7176A is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel
data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately
before and after each line during active picture and retrace. Mode 0 is illustrated in Figure 14. T he
HSYNC
, FIELD/
VSYNC
and
BLANK
(if not used) pins should be tied high during this mode.
相關(guān)PDF資料
PDF描述
ADV7175AKS High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder
ADV7176A High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder
ADV7176AKS High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder
ADV7176A* High Quality. 10-Bit. Digital CCIR-601 to PAL/NTSC Video Encoder
ADV7175 Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7175AKS 制造商:AD 制造商全稱:Analog Devices 功能描述:High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder
ADV7175KS 制造商:AD 制造商全稱:Analog Devices 功能描述:Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder
ADV7176 制造商:AD 制造商全稱:Analog Devices 功能描述:Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder
ADV7176A 制造商:AD 制造商全稱:Analog Devices 功能描述:High Quality, 10-Bit, Digital CCIR-601 to PAL/NTSC Video Encoder
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