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ADV7174/ADV7179
TABLE OF CONTENTS
Specifications.....................................................................................4
Rev. A | Page 2 of 52
2.8 V Specifications......................................................................4
2.8 V Timing Specifications........................................................5
3.3 V Specifications......................................................................6
3.3 V Timing Specifications........................................................7
Absolute Maximum Ratings............................................................9
ESD Caution..................................................................................9
Pin Configuration and Function Descriptions...........................10
General Description.......................................................................11
Data Path Description................................................................11
Internal Filter Response.............................................................11
Typical Performance Characteristics...........................................13
Features............................................................................................16
Color Bar Generation ................................................................16
Square Pixel Mode......................................................................16
Color Signal Control..................................................................16
Burst Signal Control...................................................................16
NTSC Pedestal Control .............................................................16
Pixel Timing Description..........................................................16
8-Bit YCrCb Mode .................................................................16
Subcarrier Reset..........................................................................16
Real-Time Control.....................................................................16
Video Timing Description....................................................16
Vertical Blanking Data Insertion..........................................17
Mode 0 (CCIR-656): Slave Option.......................................17
Mode 0 (CCIR-656): Master Option ...................................17
Mode 1: Slave Option HSYNC, BLANK, FIELD................20
Mode 1: Master Option HSYNC, BLANK, FIELD............21
Mode 2: Slave Option HSYNC, VSYNC, BLANK..............22
Mode 2: Master Option HSYNC, VSYNC, BLANK..........23
Mode 3: Master/Slave Option HSYNC, BLANK, FIELD.. 24
Power-On Reset.......................................................................... 25
SCH Phase Mode........................................................................ 25
MPU Port Description............................................................... 25
Register Accesses........................................................................ 26
Register Programming................................................................... 27
Subaddress Register (SR7–SR0) ............................................... 27
Register Select (SR5–SR0)......................................................... 27
Mode Register 1 (MR1)............................................................. 29
Mode Register 2 (MR2)............................................................. 30
Mode Register 3 (MR3)............................................................. 31
Mode Register 4 (MR4)............................................................. 32
Timing Mode Register 0 (TR0)................................................ 33
Timing Mode Register 1 (TR1)................................................ 34
Subcarrier Frequency Registers 3–0........................................ 35
Subcarrier Phase Register.......................................................... 35
Closed Captioning Even Field Data Registers 1–0 ................ 35
Closed Captioning Odd Field Data Registers 1–0................. 36
NTSC Pedestal/PAL Teletext Control Registers 3–0............. 36
Teletext Request Control Register (TC07).............................. 37
CGMS_WSS Register 0 (C/W0)............................................... 37
CGMS_WSS Register 1 (C/W1)............................................... 38
CGMS_WSS Register 2 (C/W2)............................................... 38
Appendix 1—Board Design and Layout Considerations.......... 39
Ground Planes............................................................................ 39
Power Planes............................................................................... 39
Supply Decoupling..................................................................... 40
Digital Signal Interconnect....................................................... 40
Analog Signal Interconnect....................................................... 40
Appendix 2—Closed Captioning................................................. 41