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| 型號： | ADV7174KCP-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Chip Scale PAL/NTSC Video Encoder with Advanced Power Management |
| 中文描述： | COLOR SIGNAL ENCODER, QCC40 |
| 封裝： | 6 X 6 MM, MO-220VJJD-2, LFCSP-40 |
| 文件頁數(shù)： | 32/52頁 |
| 文件大?。?/td> | 488K |
| 代理商： | ADV7174KCP-REEL |
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ADV7174/ADV7179
MODE REGISTER 4 (MR4)
Bits:
Address:
Rev. A | Page 32 of 52
MR47–MR40
SR4–SR0 = 04H
Mode Register 4 is an 8-bit-wide register. Figure 42 shows the various operations under the control of Mode Register 4.
MR41
MR40
MR47
MR42
MR44
MR43
MR45
MR46
OUTPUT SELECT
MR40
0
1
YC OUTPUT
RGB/YPbPr OUTPUT
RGB SYNC
MR42
0
1
DISABLE
ENABLE
PEDESTAL
CONTROL
0
1
PEDESTAL OFF
PEDESTAL ON
MR44
SLEEP MODE
CONTROL
MR46
0
1
DISABLE
ENABLE
ACTIVE VIDEO
FILTER CONTROL
MR45
0
1
DISABLE
ENABLE
MR47
(0)
ZERO SHOULD
BE WRITTEN TO
THIS BIT
VSYNC_3H
MR43
0
1
DISABLE
ENABLE
RGB/YUV
CONTROL
0
1
RGB OUTPUT
YPbPr OUTPUT
MR41
0
Figure 42. Mode Register 4
Table 14. MR4 Bit Description
Bit Name
Output Select
RGB/YPbPr Control
RGB Sync
Bit No.
MR40
MR41
MR42
Description
This bit specifies if the part is in composite video or RGB/YPbPr mode.
This bit enables the output from the RGB DACs to be set to YPbPr output video standard.
This bit is used to set up the RGB outputs with the sync information encoded on all RGB
outputs.
When this bit is enabled (1) in slave mode, it is possible to drive the VSYNC active low
input for 2.5 lines in PAL mode and three lines in NTSC mode. When this bit is enabled in
master mode, the ADV7174/ADV7179 outputs an active low VSYNC signal for three lines
in NTSC mode and 2.5 lines in PAL mode.
This bit specifies whether a pedestal is to be generated on the NTSC composite video
signal. This bit is invalid if the ADV7174/ ADV7179 is configured in PAL mode.
This bit controls the filter mode applied outside the active video portion of the line. This
filter ensures that the sync rise and fall times are always on spec regardless of which luma
filter is selected. A Logic 1 enables this mode.
When this bit is set (1), sleep mode is enabled. With this mode enabled, the
ADV7174/ADV7179 power consumption is reduced to typically 200 nA. The I
2
C registers
can be written to and read from when the ADV7174/ADV7179 is in sleep mode. If MR46 is
set to a (0) when the device is in sleep mode, the ADV7174/ADV7179 comes out of sleep
mode and resumes normal operation. Also, if the RESET signal is applied during sleep
mode, the ADV7174/ADV7179 comes out of sleep mode and resumes normal operation.
A Logic 0 should be written to this bit.
VSYNC_3H
MR43
Pedestal Control
MR44
Active Video Filter Control
MR45
Sleep Mode Control
MR46
Reserved
MR47
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