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參數(shù)資料
| 型號： | ADV7172KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power Management |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP48 |
| 封裝： | PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 28/59頁 |
| 文件大?。?/td> | 455K |
| 代理商： | ADV7172KST |
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ADV7172/ADV7173
–28–
REV. A
MODE REGISTER 2 MR2 (MR27–MR20)
(Address (SR4–SR0) = 02H)
Mode Register 2 is an 8-bit-wide register.
Figure 46 shows the various operations under the control of
Mode Register 2.
MR2 BIT DESCRIPTION
RGB/YUV Control (MR20)
This bit enables the output from the small or large DACs to be
set to YUV or RGB output video standard.
Large DACs Control (MR21)
This bit controls the output from DACs A, B and C. When this
bit is set to “1,” composite, luma and chroma signals are output
from DACs A, B and C (respectively). When this bit is set to
“0,” RGB or YUV may be output from these DACs.
DAC Switching Control (MR22)
This bit is used to switch the DAC outputs from SCART to a
EuroSCART configuration. A complete table of all DAC output
configurations is shown in Table III.
Pedestal Control (MR23)
This bit specifies whether a pedestal is to be generated on the
NTSC composite video signal. This bit is invalid if the ADV7172/
ADV7173 is configured in PAL mode.
Square Pixel Mode Control (MR24)
This bit is used to set up square pixel mode. This is available in
slave mode only. For NTSC, a 24.54 MHz clock must be
supplied. For PAL, a 29.5 MHz clock must be supplied.
Standard I
2
C Control (MR25)
This bit controls the video standard used by the ADV7172/
ADV7173. When this bit is set to “1,” the video standard bits
programmed in Mode Register 0, Bits 0–1, indicate the video
standard. When this bit is set to “0,” the ADV7172/ADV7173
is forced into the standard selected by the NTSC_PAL pin.
Pixel Data Valid Control (MR26)
After reset, this bit has the value “0” and the pixel data input to
the encoder is blanked such that a black screen is output from
the DACs. The ADV7172/ADV7173 will be set to master mode
timing. When this bit is set to “1” by the user (via the I
2
C),
pixel data passes to the pins and the encoder reverts to the
timing mode defined by Timing Mode Register 0.
Sleep Mode Enable Bit (MR27)
When this bit is set (“1”), sleep mode is enabled. With this
mode enabled the ADV7172/ADV7173 power consumption is
reduced to less than 20
μ
A. The I
2
C registers can be written to
and read from when the ADV7172/ADV7173 is in sleep mode.
If “0” is written to MR27 when the device is in sleep mode, the
ADV7172/ADV7173 will come out of sleep mode and resume
normal operation. Also, if the reset signal is applied during
sleep mode, the ADV7172/ADV7173 will come out of sleep
mode and resume normal operation. This mode will only oper-
ate when MR60 is set to a Logic “1,” otherwise sleep mode is
controlled by the PAL_NTSC and SCRESET/RTC pin.
MR21
MR27
MR22
MR23
MR26
MR25
MR24
MR20
SLEEP MODE
CONTROL
MR27
0
1
DISABLE
ENABLE
STANDARD I
2
C
CONTROL
MR25
0
1
DISABLE
ENABLE
PIXEL DATA VALID
CONTROL
MR26
0
1
DISABLE
ENABLE
SQUARE PIXEL
CONTROL
MR24
0
1
DISABLE
ENABLE
SCART ENABLE
CONTROL
MR22
0
1
DISABLE
ENABLE
RGB/YUV
CONTROL
0
1
RGB OUTPUT
YUV OUTPUT
MR20
PEDESTAL
CONTROL
0
1
PEDESTAL ON
PEDESTAL OFF
MR23
LARGE DACs
CONTROL
0
1
RGB/YUV/COMP
COMP/LUMA/CHROMA
MR21
Figure 46. Mode Register 2 (MR2)
Table III. DAC Output Configuration Matrix
MR22
MR21
MR20
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
G
Y
CVBS
CVBS
CVBS
CVBS
CVBS
CVBS
B
U
LUMA
LUMA
B
U
LUMA
LUMA
R
V
CHROMA
CHROMA
R
V
CHROMA
CHROMA
CVBS
CVBS
G
Y
G
Y
G
Y
LUMA
LUMA
B
U
LUMA
LUMA
B
U
CHROMA
CHROMA
R
V
CHROMA
CHROMA
R
V
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7172KST-REEL | 制造商:Analog Devices 功能描述: |
| ADV7172KSTZ | 制造商:Analog Devices 功能描述: |
| ADV7172KSTZ-REEL | 功能描述:IC DAC VIDEO NTSC 6-CH 48-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7173 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power Management |
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