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參數(shù)資料
| 型號： | ADV7172 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power Management |
| 中文描述： | 數(shù)碼PAL / NTSC視頻編碼器與六DAC的10位，色彩控制和增強的電源管理 |
| 文件頁數(shù)： | 24/59頁 |
| 文件大?。?/td> | 455K |
| 代理商： | ADV7172 |
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ADV7172/ADV7173
–24–
REV. A
SLEEP MODE
If after reset the SCRESET/RTC and NTSC_PAL pins are
both set to high, the part ADV7172/ADV7173 will power-up
in sleep mode to facilitate low power consumption before all
registers have been initialized. If Mode Register 6, Bit 0 (MR60) is
then set to (“1”) sleep mode control passes to Mode Register 2,
Bit 7 (i.e., control via I
2
C).
SCH PHASE MODE
The SCH phase is configured in default mode to reset every
four (NTSC) or eight (PAL) fields to avoid an accumulation of
SCH phase error over time. In an ideal system, zero SCH phase
error would be maintained forever, but in reality, this is impos-
sible to achieve due to clock frequency variations. This effect is
reduced by the use of a 32-bit DDS, which generates this SCH.
Resetting the SCH phase every four or eight fields avoids the
accumulation of SCH phase error, and results in very minor
SCH phase jumps at the start of the four or eight field sequence.
Resetting the SCH phase should not be done if the video source
does not have stable timing or the ADV7172/ADV7173 is con-
figured in RTC mode (MR41 = “1” and MR42 = “1”). Under
these conditions (unstable video) the subcarrier phase reset should
be enabled (MR42 = “0” and MR41 = “1”) but no reset applied.
In this configuration the SCH phase will never be reset, which
that the output video will now track the unstable input video.
The subcarrier phase reset when applied will reset the SCH
phase to Field 0 at the start of the next field (e.g., subcarrier
phase reset applied in Field 5 (PAL) on the start of the next
field SCH phase will be reset to Field 0).
CSO, HSO AND VSO OUTPUTS
The ADV7172/ADV7173 supports three timing signals, CSO
(composite sync signal), HSO (horizontal sync signal) and VSO
(vertical sync signal). These output TTL signals are aligned
with the analog video outputs. HSO and CSO are shared on Pin
10. Mode Register 7, Bit MR75 can be used to configure this
output pin. See Figure 37 for an example of these waveforms.
CLAMP OUTPUT
The ADV7172/ADV7173 has a programmable clamp TTL
output signal. The clamp signal is programmable to the front
and back porch. Mode Register 5, Bit MR57 can be used to
control the porch position. Also the position of the clamp signal
can be varied by 1–3 clock cycles in a positive and negative
direction from the default position. Mode Register 5, Bits MR56,
MR55 and MR54 control this position.
MR57 = 1
MR57 = 0
0H
Figure 38. Clamp Output Timing
MPU PORT DESCRIPTION
The ADV7172 and ADV7173 support a two wire serial (I
2
C
Compatible) microprocessor bus driving multiple peripherals.
Two inputs serial data (SDATA) and serial clock (SCLOCK)
carry information between any device connected to the bus.
Each slave device is recognized by a unique address. The
ADV7172 and ADV7173 each have four possible slave ad-
dresses for both read and write operations. These are unique
addresses for each device and are illustrated in Figure 39 and
Figure 40. The LSB sets either a read or write operation.
Logic Level “1” corresponds to a read operation while Logic
Level “0” corresponds to a write operation. A1 is set by setting
the ALSB pin of the ADV7172/ADV7173 to Logic Level “0”
or Logic Level “1.” When ALSB is set to “0,” there is greater
bandwidth on the I
2
C lines, which allows high speed data trans-
fers on this bus. When ALSB is set to “1,” there is reduced
input bandwidth on the I
2
C lines which means that impulses of
less than 50 ns will not pass into the I
2
C internal controller.
This mode is recommended for noisy systems.
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
0
1
WRITE
READ
1
1
0
1
0
1
A1
X
Figure 39. ADV7172 Slave Address
VSO
HSO
CSO
OUTPUT
VIDEO
525
1
2
3
4
5
6
7
8
9
10
11-19
EXAMPLE: NTSC
Figure 37. CSO, HSO, VSO Timing Diagram
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|---|---|
| ADV7172KST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power Management |
| ADV7172KST-REEL | 制造商:Analog Devices 功能描述: |
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| ADV7172KSTZ-REEL | 功能描述:IC DAC VIDEO NTSC 6-CH 48-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標準包裝:1 系列:- 類型:編碼器 應用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應商設備封裝:模塊 包裝:散裝 其它名稱:Q4645799 |
| ADV7173 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Digital PAL/NTSC Video Encoder with Six DACs 10 Bits, Color Control and Enhanced Power Management |
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