參數(shù)資料
型號(hào): ADV7162KS170
廠商: ANALOG DEVICES INC
元件分類: 顯示控制器
英文描述: 96-Bit, 220 MHz True-Color Video RAM-DAC
中文描述: 1600 X 1200 PIXELS PALETTE-DAC DSPL CTLR, PQFP160
封裝: PLASTIC, QFP-160
文件頁數(shù): 22/44頁
文件大?。?/td> 668K
代理商: ADV7162KS170
REV. 0
–22–
ADV7160/ADV7162
Figure 33. MPU Port and Register Configuration
MICROPROCESSOR (MPU PORT)
The ADV7160/ADV7162 supports a standard MPU Interface.
All the functions of the part are controlled via this MPU port.
Direct access is gained to the Address Register, Mode Register
and all the Control Registers as well as the Color Palette. The
following sections describe the setup for reading and writing to
all of the devices registers.
MPU Interface
The MPU interface (Figure 33) consists of a bidirectional, 10-
bit wide databus and interface control signals
CE
, C0, C1 and
R
/W
. The 10-bit wide databus is user configurable as illustrated.
Table I. Data-Bus Width
Data-Bus
Width
RAM/DAC
Resolution
Read/Write
Mode
10-Bit
10-Bit
8-Bit
8-Bit
10-Bit
8-Bit
10-Bit
8-Bit
10-Bit Parallel
8-Bit Parallel
8 + 2 Byte
8-Bit Parallel
Register Mapping
The ADV7160/ADV7162 contains a number of on-board regis-
ters including the Mode Register (MR17–MR10), Address Reg-
ister (A10–A0) and many Control Registers as well as Color
Palette Registers. These registers control the entire operation of
the part. Figure 34 shows the internal register configuration.
Control lines C1 and C0 determine which register the MPU is
accessing. C1 and C0 also determine whether the Address Reg-
ister is pointing to the color registers and Look-Up Table RAM
or the control registers. If C1, C0 = 1, 0 the MPU has access to
whatever control register is pointed to by the Address Register
(A10–A0). If C1, C0 = 0, 1 the MPU has access to the Look-
Up Table RAM (Color Palette) or the Overlay Palette through
the associated color registers. The
CE
input latches data to or
from the part.
The R/
W
control input determines between read or write ac-
cesses. The truth tables show all modes of access to the various
registers and color palette for both the 8-bit wide databus con-
figuration and 10-bit wide data bus configuration. It should be
noted that after power-up, the devices MPU port is automati-
cally set to 10-bit wide operation (see Power-On Reset section).
Figure 32. 8-Bit Pseudo Color in 8:1 Multiplexing Mode
The unused Blue pixel inputs are used, in this mode, to provide
8 extra PS inputs. These PS inputs provide 2 bits after 8:1 mul-
tiplexing. The PS inputs can be used as Overlay or Palette Se-
lect inputs.
2
PS
P
I
X
E
L
I
N
P
U
T
M
U
L
T
I
P
L
E
X
E
R
G7–G0
R7–R0
G7–G0
R7–R0
G7–G0
R7–R0
G7–G0
R7–R0
PS1–PS0
B1–B0
PS1–PS0
B1–B0
PS1–PS0
B1–B0
PS1–PS0
B1–B0
A
B
C
D
E
F
G
H
A
B
C
D
E
F
G
H
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8-BIT COLOR
DATA
24-BIT TO 30-BIT
LOOK-UP-TABLE
30-BIT COLOR
DATA
ANALOG VIDEO
OUTPUTS
RED
256 x 10
10
10
10
10-BIT
RED
DAC
10-BIT
GREEN
DAC
10-BIT
BLUE
DAC
RED
OUT
GREEN
OUT
BLUE
OUT
8
GREEN
256 x 10
BLUE
256 x 10
MPU PORT
C0
CE
R/W
10 (8+2)
RED
REGISTER
DATA TO
PALETTES
30
CURSOR
REGISTERS
TEST
REGISTERS
ID
REGISTER
STATUS
REGISTER
PIXEL MASK
REGISTER
REVISION
REGISTER
PLL
REGISTERS
COMMAND
REGISTERS
(CR1–CR5)
C1
D9–D0
ADDRESS
REGISTER
MODE
REGISTER
GREEN
REGISTER
BLUE
REGISTER
CONTROL REGISTERS
COLOR REGISTERS
C1 C0
1 1
ADDR
(A10-A0)
(MRI)
C1 C0
0 1
C1 C0
0 0
C1 C0
1 0
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