參數(shù)資料
型號(hào)： ADV7152LS85
廠商： ANALOG DEVICES INC
元件分類： 顯示控制器
英文描述： CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC
中文描述： PALETTE-DAC DSPL CTLR, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 9/32頁(yè)
文件大小： 454K
代理商： ADV7152LS85
ADV7152
–9–
REV. B
Mnemonic
Function
R/
W
Read/Write Control (T T L Compatible Input). T his input determines whether data is
written to or read from the device’s registers and color palette RAM. R/
W
and
CE
must
be at Logic “0” to write data to the part. R/
W
must be at Logic “1” and
CE
at Logic
“0” to read from the device.
Command Controls (T T L Compatible Inputs). T hese inputs determine the type of read
or write operation being performed on the device over the databus (see Interface T ruth
T able). Data on these inputs is latched on the falling edge of
CE
.
Red, Green and Blue Current Outputs (High Impedance Current Sources). T hese RGB
video outputs are specified to directly drive RS-343A and RS-170 video levels into dou-
bly terminated 75
loads.
IOR
,
IOG
and
IOB
are the complementary outputs of IOR, IOG and IOB. T hese out-
puts can be tied to GND if it is not required to use differential outputs.
Voltage Reference Input (Analog Input). An external 1.235 V voltage reference is re-
quired to drive this input. An AD589 (2-terminal voltage reference) or equivalent is rec-
ommended. (Note: It is not recommended to use a resistor network to generate the
voltage reference.)
Output Full-Scale Adjust Control (Analog Input). A resistor connected between this pin
and analog ground controls the absolute amplitude of the output video signal. T he value
of R
SET
is derived from the full-scale output current on IOG according to the following
equations:
R
SET
(
) = C1
×
R
REF
/IOG (mA);
SYNC
on GREEN
R
SET
(
) = C2
×
R
REF
/IOG (mA); No
SYNC
on GREEN.
Full-Scale output currents on IOR and IOB for a particular value of R
SET
are given by:
IOR
(
mA
)=
C
2
×
R
REF
(V)/R
SET
(
)
and
IOB
(
mA
) =
C
2
×
R
REF
(V)/R
SET
(
)
where
C
1 = 6,050: PEDEST AL = 7.5 IRE
where C1
= 5,723: PEDEST AL = 0 IRE
and
where
C
2 = 4,323: PEDEST AL = 7.5 IRE
where C1
= 3,996: PEDEST AL = 0 IRE.
Compensation Pin. A 0.1
μ
F capacitor should be connected between this pin and V
AA
.
Phase Lock Loop Output Current (High Impedance Current Source). T his output is
used to enable multiple ADV7150/ADV7152s along with ADV7151s to be synchronized
together with subpixel resolution when using an external PLL. T his output is triggered
either from the falling edge of
SYNC
or
BLANK
as determined by bit CR21 of Com-
mand Register 2. When activated, it supplies a current corresponding to
I
PLL
(
mA
) = 1,728
×
R
REF
(
V
)/
R
SET
(
)
When not using the I
PLL
function, this output pin should be tied to GND.
Power Supply (+5 V
±
5%). T he part contains multiple power supply pins, all should be
connected together to one common +5 V filtered analog power supply.
Analog Ground. T he part contains multiple ground pins, all should be connected
together to the system’s ground plane.
C0, C1
IOR;
IOR
, IOG;
IOG
, IOB;
IOB
V
REF
R
SET
COMP
I
PLL
V
AA
GND
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