參數(shù)資料
型號(hào): ADV7152LS170
廠商: ANALOG DEVICES INC
元件分類: 顯示控制器
英文描述: CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC
中文描述: PALETTE-DAC DSPL CTLR, PQFP100
封裝: PLASTIC, QFP-100
文件頁數(shù): 19/32頁
文件大?。?/td> 454K
代理商: ADV7152LS170
ADV7152
–19–
REV. B
DAC T est Register
(Address Reg (A7–A0) = 01H)
T his register is used when the device is in test/diagnostic mode.
It is a 30-bit (10 bits each for RED, GREEN and BLUE) wide
read-only register which allows MPU access to the DAC port,
see “T est Diagnostic” section.
SYNC
,
BLANK
and I
PLL
T est Register
(Address Reg (A7–A0) = 02H)
T his register is used when the device is in test/diagnostic mode.
It is a 3-bit wide (3 LSBs) read/write register which allows
MPU access to these particular pixel control bits, see “T est
Diagnostic” section.
ID Register
(Address Reg (A7–A0) = 03H)
T his is an 8-bit wide “Identification” read-only register. For the
ADV7152 it will always return the hexadecimal value 8CH.
Pixel Mask Register (Address Reg (A7–A0) = 04H)
T he contents of the pixel mask register are individually bit-wise
logically AND-ed with the Red, Green and Blue pixel input
stream of data. It is an 8-bit read/write register with D0 corre-
sponding to R0, G0 and B0. For normal operation, this register
is set with FFH.
COMMAND RE GIST E R 1 (CR1)
(Address Reg (A7–A0) = 05H)
T his register contains a number of control bits as shown in the
diagram. CR1 is a 10-bit wide register. However for program-
ming purposes, it may be considered as an 8-bit wide register
(CR18 to CR19 are reserved).
T he diagram below shows the various operations under the con-
trol of CR1. T his register can be read from as well as written to. In
write mode, “0” should be written to CR11 and CR13–CR17.
In read mode, CR11 and CR13–CR19 are returned as zeros.
COMMAND RE GIST E R 1 BIT DE SCRIPT ION
Calibration Control (CR10)
T his bit automatically calibrates the onboard L OAD IN/
LOADOUT synchronization circuit. MR15 of Mode Register
MR1 must be set to “0.”
SYNCOUT
Control (CR12)
T his bit specified whether the video
SYNCOUT
signal is to be
enabled. On power up a “0” is written to the bit and
SYNCOUT
” is set three-state.
CR12
0 DISABLE
1 ENABLE
SYNCOUT
SYNCOUT CONTROL
CR12
CR11
CR10
CALIBRATION CONTROL
CR10
0 DISABLE
1 CALIBRATES
ON EVERY
VERTICAL
SYNC
(MR15=0)
CR11
(0)
THIS BIT
SHOULD BE
SET TO ZERO
CR17–CR13
(00000)
THESE BITS
SHOULD BE
SET TO ZERO
CR13
CR14
CR15
CR16
CR17
CR18
CR19
RESERVED
*
THESE BITS ARE READ-ONLY RESERVED BITS.
A READ CYCLE WILL RETURN ZEROS "00."
*
Command Register 1 (CR1) (CR19–CR10)
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