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參數(shù)資料
| 型號(hào)： | ADV7152LS110 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顯示控制器 |
| 英文描述： | CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC |
| 中文描述： | PALETTE-DAC DSPL CTLR, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 15/32頁(yè) |
| 文件大小： | 454K |
| 代理商： | ADV7152LS110 |
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ADV7152
–15–
REV. B
PIXEL
DATA
PIN
MENTS
LDATA
TO
PIXEL
PORT
DATA
INTERNALLY
SHIFTED
TO 5 LSBS
B7
B6
B5
B4
B3
B2
B1
B0
x
x
x
x
x
x
x
x
R7
R6
R5
R4
R3
R2
R1
R0
R4
R3
R2
R1
R0
G4
G3
G2
G4
G3
G2
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
x
G1
G0
B4
B3
B2
B1
B0
B2
B1
B0
x
G1
G0
B4
B3
DATA LATCHES
FIRST 32
LOF RAM
5
10
TO
BLUE
DAC
0
0
0
B4
B3
B2
B1
B0
LOCATION "0"
LOCATION "31"
256 x 10 RAM
(BLUE LUT)
TO
RED
10
0
0
0
R4
R3
R2
R1
R0
256 x 10 RAM
(RED LUT)
LOCATION "0"
LOCATION "31"
TO
GREEN
DAC
10
G4
G3
G2
G1
G0
0
0
0
256 x 10 RAM
(GREEN LUT)
LOCATION "0"
LOCATION "31"
5
5
x
x
x
x
x
x
x
x
Figure 24. 15-Bit True-Color Mapping Using R0–R7
and G0–G6
MICROPROCE SSOR (MPU) PORT
T he ADV7152 supports a standard MPU Interface. All the
functions of the part are controlled via this MPU port. Direct
access is gained to the Address Register, Mode Register and all
the Control Registers as well as the Color Palette. T he follow-
ing sections describe the setup for reading and writing to all of
the devices registers.
MPU Interface
T he MPU interface (Figure 25) consists of a bidirectional,
10-bit wide databus and interface control signals
CE
, C0, C1
and R/
W
. T he 10-bit wide databus is user configurable as
illustrated.
T able II. Databus Width T able
Databus
Width
RAM/DAC
Resolution
Read/Write
Mode
10 Bit
10 Bit
8 Bit
8 Bit
10 Bit
8 Bit
10 Bit
8 Bit
10-Bit Parallel
8-Bit Parallel
8+2 Byte
8-Bit Parallel
Register Mapping
T he ADV7152 contains a number of onboard registers includ-
ing the Mode Register (MR17–MR10), Address Register (A7–
A0) and nine Control Registers as well as Red (R9–R0), Green
(G9–G0) and Blue (B9–B0) Color Registers. T hese registers
control the entire operation of the part. Figure 26 shows the
internal register configuration.
Control lines C1 and C0 determine which register the MPU is
accessing. C1 and C0 also determine whether the Address Reg-
ister is pointing to the color registers and look-up table RAM or
the control registers. If C1, C0 = 1, 0, the MPU has access to
whatever control register is pointed to by the Address Register
(A7–A0). If C1, C0 = 0, 1, the MPU has access to the Look-Up
T able RAM (Color Palette) through the associated color regis-
ters. T he
CE
input latches data to or from the part.
T he R/
W
control input determines between read or write ac-
cesses. T he T ruth T ables III and IV show all modes of access to
the various registers and color palette for both the 8-bit wide
databus configuration and 10-bit wide databus configuration. It
should be noted that after power-up, the devices MPU port is
automatically set to 10-bit wide operation (see Power-On Reset
section).
Color Palette Accesses
Data is written to the color palette by first writing to the address
register of the color palette location to be modified. T he MPU
performs three successive write cycles for each of the red, green
and blue registers (10 bit or 8 bit). An internal pointer moves
from red to green to blue after each write is completed. T his
pointer is reset to red after a blue write or whenever the address
register is written. During the blue write cycle, the three bytes of
red, green and blue are concatenated into a single 30-bit/24-bit
word and written to the RAM location as specified in the ad-
dress register (A7–A0). T he address register then automatically
increments to point to the next RAM location and a similar red,
green and blue palette write sequence is performed. T he address
register resets to 00H following a blue write cycle to color pal-
ette RAM location FFH.
30
MPU PORT
D0 – D9
10 (8+2)
C0
C1
COMMAND
REGISTERS
(CR1–CR3)
(MR1)
DATA TO
PALETTES
CONTROL REGISTERS
COLOR REGISTERS
ADDRESS
REGISTER
MODE
REGISTER
ID
REGISTER
BLUE
REGISTER
CE
R/W
GREEN
REGISTER
RED
REGISTER
PIXEL MASK
REGISTER
TEST
REGISTERS
REVISION
REGISTER
ADDR
(A7–A0)
Figure 25. MPU Port and Register Configuration
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV7152LS135 | CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC |
| ADV7152LS170 | CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC |
| ADV7152LS220 | CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC |
| ADV7160 | 96-Bit, 220 MHz True-Color Video RAM-DAC(96位,220MHz,真彩色視頻RAM-D/A轉(zhuǎn)換器) |
| ADV7162 | 96-Bit, 220 MHz True-Color Video RAM-DAC(96位,220MHz,真彩色視頻RAM-D/A轉(zhuǎn)換器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7152LS135 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADV7152LS170 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC |
| ADV7152LS220 | 制造商:Analog Devices 功能描述: 制造商:Analog Devices 功能描述:PALETTE-DAC DSPL CTLR, PQFP100 |
| ADV7152LS85 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC |
| ADV7160 | 制造商:AD 制造商全稱:Analog Devices 功能描述:96-Bit, 220 MHz True-Color Video RAM-DAC |
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