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參數(shù)資料
| 型號： | ADV7125 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CMOS, 330 MHz Triple 8-Bit High Speed Video DAC |
| 中文描述： | 的CMOS，330 MHz的三路8位高速視頻DAC |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 264K |
| 代理商： | ADV7125 |
REV. 0
ADV7125
–5–
3.3 V TIMING SPECIFICATIONS
1
(V
AA
= 3.0 V to 3.6 V
2
, V
REF
= 1.235 V, R
SET
= 560
to T
MAX3
, unless otherwise noted, T
J MAX
= 110 C.)
, C
L
= 10 pF. All specifications T
MIN
Parameter
Min
Typ
Max
Unit
Condition
ANALOG OUTPUTS
Analog Output Delay, t
6
Analog Output Rise/Fall Time, t
74
Analog Output Transition Time, t
85
Analog Output Skew, t
96
CLOCK CONTROL
f
CLK7
f
CLK7
f
CLK7
f
CLK7
Data and Control Setup, t
16
Data and Control Hold, t
26
Clock Period, t
3
Clock Pulsewidth High, t
46
Clock Pulsewidth Low, t
56
Clock Pulsewidth High, t
46
Clock Pulsewidth Low, t
56
Clock Pulsewidth High, t
46
Clock Pulsewidth Low, t
56
Clock Pulsewidth High, t
4
Clock Pulsewidth Low, t
5
Pipeline Delay, t
PD6
PSAVE Up Time, t
106
7.5
1.0
15
1
ns
ns
ns
ns
2
50
140
240
330
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycles
ns
50 MHz Grade
140 MHz Grade
240 MHz Grade
330 MHz Grade
0.2
1.5
3
1.4
1.4
1.875
1.875
2.85
2.85
8.0
8.0
1.0
f
CLK_MAX
= 330 MHz
f
CLK_MAX
= 330 MHz
f
CLK_MAX
= 240 MHz
f
CLK_MAX
= 240 MHz
f
CLK_MAX
= 140 MHz
f
CLK_MAX
= 140 MHz
f
CLK_MAX
= 50 MHz
f
CLK_MAX
= 50 MHz
1.0
4
1.0
10
NOTES
1
Timing specifications are measured with input levels of 3.0 V (V
) and 0 V (V
IL
) for 3.3 V supplies.
2
These maximum and minimum specifications are guaranteed over this range.
3
Temperature range: T
to T
: –40
°
C to +85
°
C at 50 MHz and 140 MHz, 0
°
C to +70
°
C at 240 MHz and 330 MHz.
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
f
CLK
max specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.
Specifications subject to change without notice.
t
2
CLOCK
DATA
NOTES
1. OUTPUT DELAY (
t
) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK TO THE 50% POINT
OF FULL-SCALE TRANSITION.
2. OUTPUT RISE/FALL TIME (
t
) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION.
3. TRANSITION TIME (
t
) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF THE
FINAL OUTPUT VALUE.
ANALOG OUTPUTS
(IOR,
IOR
, IOG,
IOG
, IOB,
IOB
)
DIGITAL INPUTS
(R7–R0, G7–G0, B7–B0,
SYNC
,
BLANK
)
t
3
t
4
t
5
t
1
t
8
t
6
t
7
Figure 1. Timing Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7125_11 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS, 330 MHz Triple 8-Bit High Speed Video DAC |
| ADV7125BCPZ170 | 功能描述:IC DAC VIDEO 3CH 330MHZ 48VFQFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| ADV7125BCPZ170-RL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| ADV7125JST240 | 制造商:Analog Devices 功能描述:DAC 3-CH Segment 8-bit 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:8-BITTRIPLE HS VIDEO DAC (50-330MHZ)I.C. - Bulk 制造商:Analog Devices 功能描述:IC 8-BIT VIDEO DAC 制造商:Analog Devices 功能描述:PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PQFP48 |
| ADV7125JST330 | 制造商:Analog Devices 功能描述:DAC 3-CH Segment 8-bit 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:8-BITTRIPLE HS VIDEO DAC (50-330MHZ)I.C. - Bulk |
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