參數(shù)資料
型號: ADV7122KST50
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: CMOS 80 MHz, Triple 10-Bit Video DACs
中文描述: PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PQFP48
封裝: 1.40 MM HEIGHT, PLASTIC, TQFP-48
文件頁數(shù): 7/12頁
文件大?。?/td> 196K
代理商: ADV7122KST50
ADV7121/ADV7122
–7–
REV. B
T E RMINOLOGY
Blanking Level
T he level separating the
SYNC
portion from the video portion
of the waveform. Usually referred to as the front porch or back
porch. At 0 IRE units, it is the level which will shut off the pic-
ture tube, resulting in the blackest possible picture.
Color Video (RGB)
T his usually refers to the technique of combining the three pri-
mary colors of red, green and blue to produce color pictures
within the usual spectrum. In RGB monitors, three DACs are
required, one for each color.
Sync Signal (
SYNC
)
T he position of the composite video signal which synchronizes
the scanning process.
Gray Scale
T he discrete levels of video signal between reference black and
reference white levels. A 10-bit DAC contains 1024 different
levels, while an 8-bit DAC contains 256.
Raster Scan
T he most basic method of sweeping a CRT one line at a time to
generate and display images.
Reference Black Level
T he maximum negative polarity amplitude of the video signal.
Reference White Level
T he maximum positive polarity amplitude of the video signal.
Sync Level
T he peak level of the
SYNC
signal.
Video Signal
T hat portion of the composite video signal which varies in gray
scale levels between reference white and reference black. Also
referred to as the picture signal, this is the portion which may be
visually observed.
CIRCUIT DE SCRIPT ION & OPE RAT ION
T he ADV7121/ADV7122 contains three 10-bit D/A converters,
with three input channels, each containing a 10-bit register.
Also integrated on board the part is a reference amplifier. CRT
control functions
BLANK
and
SYNC
are integrated on board
the ADV7122.
Digital Inputs
T hirty bits of pixel data (color information) R0–R9, G0–G9 and
B0–B9 are latched into the device on the rising edge of each
clock cycle. T his data is presented to the three 10-bit DACs and
is then converted to three analog (RGB) output waveforms. See
Figure 2.
T he ADV7122 has two additional control signals, which are
latched to the analog video outputs in a similar fashion.
BLANK
and
SYNC
are each latched on the rising edge of CLOCK to
maintain synchronization with the pixel data stream.
T he
BLANK
and
SYNC
functions allow for the encoding of
these video synchronization signals onto the RGB video output.
T his is done by adding appropriately weighted current sources
to the analog outputs, as determined by the logic levels on the
BLANK
and
SYNC
digital inputs. Figure 3 shows the analog
output, RGB video waveform of the ADV7121/ADV7122. T he
influence of
SYNC
and
BLANK
on the analog video waveform
is illustrated.
T able I details the resultant effect on the analog outputs of
BLANK
and
SYNC
.
All these digital inputs are specified to accept T T L logic levels.
Clock Input
T he CLOCK input of the ADV7121/ADV7122 is typically the
pixel clock rate of the system. It is also known as the dot rate.
T he dot rate, and hence the required CLOCK frequency, will be
determined by the on-screen resolution, according to the follow-
ing equation:
Dot Rate
= (
Horiz Res
)
×
(
Vert Res
)
×
(
Refresh Rate
)/
(
Retrace Factor
)
Horiz Res
= Number of Pixels/Line.
Vert Res
= Number of Lines/Frame.
Refresh Rate
= Horizontal Scan Rate. T his is the rate at
which the screen must be refreshed, typ-
ically 60 Hz for a noninterlaced system or
30 Hz for an interlaced system.
Retrace Factor
= T otal Blank T ime Factor. T his takes into
account that the display is blanked for a
certain fraction of the total duration of
each frame (e.g., 0.8).
CLOCK
DATA
DIGITAL INPUTS
(R0–R9, G0–G9, B0–B9;
SYNC, BLANK)
ANALOG OUTPUTS
(IOR, IOG, IOB)
Figure 2. Video Data Input/Output
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