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參數(shù)資料
| 型號： | ADV7122KP80 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | CMOS 80 MHz, Triple 10-Bit Video DACs |
| 中文描述： | TRIPLE, PARALLEL, 8 BITS INPUT LOADING, 10-BIT DAC, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 196K |
| 代理商： | ADV7122KP80 |
ADV7121/ADV7122
–10–
REV. B
More detailed information regarding load terminations for vari-
ous output configurations, including RS-343A and RS-170, is
available in an Application Note entitled “Video Formats &
Required Load T erminations” available from Analog Devices,
publication no. E1228–15–1/89.
Figure 3 shows the video waveforms associated with the three
RGB outputs driving the doubly terminated 75
load of Fig-
ure 5a. As well as the gray scale levels, Black Level to White
Level, the diagram also shows the contributions of
SYNC
and
BLANK
for the ADV7122. T hese control inputs add appropri-
ately weighted currents to the analog outputs, producing the
specific output level requirements for video applications.
T able Ia. details how the
SYNC
and
BLANK
inputs modify
the output levels.
Gray Scale Operation
T he ADV7121/ADV7122 can be used for stand-alone, gray
scale (monochrome) or composite video applications (i.e., only
one channel used for video information). Any one of the three
channels, RED, GREEN or BLUE can be used to input the
digital video data. T he two unused video data channels should
be tied to logical zero. T he unused analog outputs should be
terminated with the same load as that for the used channel. In
other words, if the red channel is used and IOR is terminated
with a doubly terminated 75
load (37.5
), IOB and IOG
should be terminated with 37.5
resistors. See Figure 6.
GND
ADV7121/ADV7122
R0
R9
G0
G9
B0
B9
VIDEO
INPUT
DOUBLY
TERMINATED
75
LOAD
IOR
IOG
IOB
37.5
37.5
Figure 6. Input and Output Connections for Stand-Alone
Gray Scale or Composite Video
Video Output Buffers
T he ADV7121/ADV7122 is specified to drive transmission line
loads, which is what most monitors are rated as. T he analog
output configurations to drive such loads are described in the
Analog Interface section and illustrated in Figure 5. However,
in some applications it may be required to drive long “transmis-
sion line” cable lengths. Cable lengths greater than 10 meters
can attenuate and distort high frequency analog output pulses.
T he inclusion of output buffers will compensate for some cable
distortion. Buffers with large full power bandwidths and gains
between 2 and 4 will be required. T hese buffers will also need
to be able to supply sufficient current over the complete output
voltage swing. Analog Devices produces a range of suitable op
amps for such applications. T hese include the AD84x series of
monolithic op amps. In very high frequency applications (80 MHz),
the AD9617 is recommended. More information on line driver
buffering circuits is given in the relevant op amp data sheets.
Use of buffer amplifiers also allows implementation of other
video standards besides RS-343A and RS-170. Altering the gain
components of the buffer circuit will result in any desired video
level.
DACs
Z
O
= 75
(CABLE)
Z
S
= 75
(SOURCE
TERMINATION)
AD848
3
+V
S
0.1
μ
F
0.1
μ
F
IOR, IOG, IOB
75
2
7
6
4
Z
1
Z
= 75
(MONITOR)
Z
1
Z
2
GAIN (G) = 1+ ––
–V
S
Z
2
Figure 7. AD848 As an Output Buffer
PC Board Layout Considerations
T he ADV7121/ADV7122 is optimally designed for lowest noise
performance, both radiated and conducted noise. T o comple-
ment the excellent noise performance of the ADV7121/ADV7122
it is imperative that great care be given to the PC board layout.
Figure 8 shows a recommended connection diagram for the
ADV7121/ADV7122.
T he layout should be optimized for lowest noise on the
ADV7121/ADV7122 power and ground lines. T his can be
achieved by shielding the digital inputs and providing good de-
coupling. T he lead length between groups of V
AA
and GND
pins should by minimized so as to minimize inductive ringing.
Ground Planes
T he ADV7121/ADV7122 and associated analog circuitry,
should have a separate ground plane referred to as the analog
ground plane. T his ground plane should connect to the regular
PCB ground plane at a single point through a ferrite bead, as il-
lustrated in Figure 8. T his bead should be located as close as
possible (within 3 inches) to the ADV7121/ADV7122.
T he analog ground plane should encompass all ADV7121/
ADV7122 ground pins, voltage reference circuitry, power sup-
ply bypass circuitry, the analog output traces and any output
amplifiers.
T he regular PCB ground plane area should encompass all the
digital signal traces, excluding the ground pins, leading up to
the ADV7121/ADV7122.
Power Planes
T he PC board layout should have two distinct power planes,
one for analog circuitry and one for digital circuitry. T he analog
power plane should encompass the ADV7121/ADV7122 (V
AA
)
and all associated analog circuitry. T his power plane should be
connected to the regular PCB power plane (V
CC
) at a single
point through a ferrite bead, as illustrated in Figure 8. T his bead
should be located within three inches of the ADV7121/ADV7122.
T he PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7121/ADV7122 power pins, voltage reference
circuitry and any output amplifiers.
T he PCB power and ground planes should not overlay portions
of the analog power plane. K eeping the PCB power and ground
planes from overlaying the analog power plane will contribute to
a reduction in plane-to-plane noise coupling.
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| ADV7122KST30 | 制造商:Analog Devices 功能描述:DAC 3-CH Segment 10-bit 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:TRIPLE 10 BIT VIDEO DAC I.C. - Bulk |
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