參數(shù)資料
型號(hào): ADV3002BSTZ-RL
廠商: Analog Devices Inc
文件頁數(shù): 4/28頁
文件大?。?/td> 0K
描述: IC SWITCH HDMI/DVI 4:1 80-LQFP
產(chǎn)品變化通告: Marking Change 25/Mar/2009
標(biāo)準(zhǔn)包裝: 1,000
功能: 開關(guān)
電路: 1 x 4:1
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 3 V ~ 3.6 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-LQFP(14x14)
包裝: 帶卷 (TR)
ADV3002
Data Sheet
Rev. B | Page 12 of 28
THEORY OF OPERATION
The primary function of the ADV3002 is to switch up to four
HDMI/DVI sources to one HDMI/DVI sink. Each HDMI/DVI
link consists of four differential, high speed channels and four
auxiliary single-ended, low speed signals. The high speed channels
include a data-word clock and three TMDS data channels running
at 10× the data-word clock frequency for data rates up to 2.25
Gbps. The four low speed control signals are the display data
channel (DDC) bus (SDA and SCL), the consumer electronics
control (CEC) line, and the hot plug detect (HPD) signal.
The ADV3002 also includes an integrated EDID SRAM,
eliminating the need for an external EDID EEPROM for each
HDMI connector. A typical HDMI multiplexer is shown in
Figure 23. The simplified implementation using the ADV3002
is shown in Figure 24.
HDMI
Rx
HDM
IA
DDC
5V
2
EDID A
HDM
IB
DDC
5V
2
EDID B
HDM
IC
DDC
5V
2
EDID C
HDM
ID
DDC
5V
2
EDID D
4:1
HDMI
MUX
07905-
003
Figure 23. Typical HDMI Multiplexer
HDMI
Rx
HDM
IA
DDC
5V
2
EXTERNAL
EDID EEPROM
OR SYSTEM
MICROCONTROLLER
HDM
IB
DDC
5V
AMUXVCC
2
HDM
IC
DDC
EDID DDC
5V
2
HDM
ID
DDC
5V
2
ADV3002
07905-
004
Figure 24. Simplified Implementation Using the ADV3002
TMDS INPUT CHANNELS
Each high speed input differential pair terminates to the 3.3 V
power supply through a pair of 50 on-chip resistors, as shown
in Figure 25. The state of the input terminations can be configured
automatically or programmed manually by setting the appropriate
bits in the TMDS input termination control register, as shown
The input equalizer can be manually configured to provide
two different levels of high frequency boost: 4 dB or 16 dB for
2.25 Gbps data. The equalizer (EQ) level defaults to 16 dB after
reset. No specific cable length is suggested for a particular
equalization setting because cable performance varies widely
between manufacturers; however, in general, the equalization of
the ADV3002 can be set to 16 dB without degrading the signal
integrity, even for short input cables.
50
CABLE
EQ
AVCC
AVEE
IN+
IN–
NOTES
1. IN+ REFERS TO IN_x_CLK+/IN_x_DATAx+ PINS.
2. IN– REFERS TO IN_x_CLK–/IN_x_DATAx– PINS.
07905-
005
Figure 25. High Speed Input Simplified Schematic
TMDS OUTPUT CHANNELS
Each high speed output differential pair is terminated to the 3.3 V
power supply through a pair of 50 on-chip resistors, as shown
in Figure 26. This termination is user-selectable; it can be
turned on or off by programming the TX_OTO bit of the TMDS
output control register, as shown in Table 10.
50
OUT+
OUT–
ESD
PROT.
AVCC
AVEE
NOTES
1. OUT+ REFERS TO OUT_CLK+ AND OUT_DATAx+ PINS.
2. OUT– REFERS TO OUT_CLK– AND OUT_DATAx– PINS.
DISABLE
IOUT
07905-
006
Figure 26. High Speed Output Simplified Schematic
The output termination resistors of the ADV3002 back
terminate the output TMDS transmission lines. These back
terminations, as recommended in the HDMI 1.4 specification,
act to absorb reflections from impedance discontinuities on the
output traces, improving the signal integrity of the output traces
and adding flexibility to how the output traces can be routed.
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