參數(shù)資料
型號(hào)： ADV3000
廠商： Analog Devices, Inc.
英文描述： 3:1 HDMI/DVI Switch with Equalization
中文描述： 3:1的HDMI / DVI接口與均衡開(kāi)關(guān)
文件頁(yè)數(shù)： 12/28頁(yè)
文件大?。?/td> 608K
代理商： ADV3000
ADV3000
THEORY OF OPERATION
INTRODUCTION
The primary function of the ADV3000 is to switch one of three
(HDMI or DVI) single-link sources to one output. Each HDMI/
DVI link consists of four differential, high speed channels and
four auxiliary single-ended, low speed control signals. The high
speed channels include a data-word clock and three transition
minimized differential signaling (TMDS) data channels run-
ning at 10× the data-word clock frequency for data rates up to
2.25 Gbps. The four low speed control signals are 5 V tolerant
bidirectional lines that can carry configuration signals, HDCP
encryption, and other information, depending upon the specific
application.
All four high speed TMDS channels in a given link are identical;
that is, the pixel clock can be run on any of the four TMDS
channels. Transmit and receive channel compensation is
provided for the high speed channels where the user can
(manually) select among a number of fixed settings.
The ADV3000 has two control interfaces. Users have the option
of controlling the part through either the parallel control
interface or the I
2
C serial control interface. The ADV3000 has
two user-programmable I
2
C slave addresses (one bit) to allow
two ADV3000s to be controlled by a single I
2
C bus. A RESET
pin is provided to restore the control registers of the ADV3000
to default values. In all cases, serial programming values over-
ride any prior parallel programming values and any use of the
serial control interface disables the parallel control interface
until the ADV3000 is reset.
INPUT CHANNELS
Each high speed input differential pair terminates to the 3.3 V
VTTI power supply through a pair of single-ended 50 Ω on-
chip resistors, as shown in Figure 25. The input terminations
can be optionally disconnected for approximately 100 ms
following a source switch. The user can program which of the
12 high speed input channels employs this feature by selectively
programming the associated RX_PT bits in the input termination
pulse register through the serial control interface. Additionally,
all the input terminations can be disconnected by programming
the RX_TO bit in the receiver settings register. By default, the
input termination is enabled. The input terminations are
enabled and cannot be switched off when programming the
ADV3000 through the parallel control interface.
Rev. 0 | Page 12 of 28
CABLE
EQ
50
50
IP_xx
IN_xx
AVEE
VTTI
0
Figure 25. High Speed Input Simplified Schematic
The input equalizer can be manually configured to provide two
different levels of high frequency boost: 6 dB or 12 dB. The user
can individually control the equalization level of all high speed
input channels by selectively programming the associated RX_EQ
bits in the receive equalizer register through the serial control
interface. Alternately, the user can globally control the equaliza-
tion level of all eight high speed input channels by setting the
PP_EQ pin of the parallel control interface. No specific cable
length is suggested for a particular equalization setting because
cable performance varies widely between manufacturers; however,
in general, the equalization of the ADV3000 can be set to 12 dB
without degrading the signal integrity, even for short input
cables. At the 12 dB setting, the ADV3000 can equalize more
than 20 meters of 24 AWG cable at 2.25 Gbps.
OUTPUT CHANNELS
Each high speed output differential pair is terminated to the
3.3 V VTTO power supply through two 50 Ω on-chip resistors
(see Figure 26). This termination is user-selectable; it can be
turned on or off by programming the TX_PTO bit of the
transmitter settings register through the serial control interface.
The output termination resistors of the ADV3000 back-terminate
the output TMDS transmission lines. These back-terminations,
as recommended in the HDMI 1.3 specification, act to absorb
reflections from impedance discontinuities on the output traces,
improving the signal integrity of the output traces and adding
flexibility to how the output traces can be routed. For example,
interlayer vias can be used to route the ADV3000 TMDS outputs
on multiple layers of the PCB without severely degrading the
quality of the output signal.
The ADV3000 output has a disable feature that places the
outputs in an inactive mode. This mode is enabled by
programming the HS_EN bit of the high speed device modes
register through the serial control interface or by setting the
PP_EN pin of the parallel control interface. Larger wire-OR’ed
arrays can be constructed using the ADV3000 in this mode.
VTTO
50
50
OPx
ONx
AVEE
DISABLE
I
OUT
0
Figure 26. High Speed Output Simplified Schematic
相關(guān)PDF資料
PDF描述
ADV3000ASTZ 3:1 HDMI/DVI Switch with Equalization
ADV3000ASTZ-RL 3:1 HDMI/DVI Switch with Equalization
ADV3000-EVALZ 3:1 HDMI/DVI Switch with Equalization
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV3000ASTZ 制造商:Analog Devices 功能描述:HDMI/DVI SWIT 80LQFP - Trays
ADV3000ASTZ-RL 制造商:Analog Devices 功能描述:HDMI/DVI SWIT 80LQFP - Tape and Reel
ADV3000-EVALZ 制造商:Analog Devices 功能描述:EVAL KIT FOR 3:1 HDMI/DVI SWIT W/ EQUALIZATION - Bulk
ADV3002 制造商:AD 制造商全稱:Analog Devices 功能描述:4:1 HDMI/DVI Switch with Equalization, DDC/CEC Buffers and EDID Replication
ADV3002BSTZ 功能描述:IC SWITCH HDMI/DVI 4:1 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開(kāi)關(guān)，多路復(fù)用器，多路分解器 系列:- 應(yīng)用說(shuō)明:Ultrasound Imaging Systems Application Note 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 功能:開(kāi)關(guān) 電路:單刀單擲 導(dǎo)通狀態(tài)電阻:48 歐姆 電壓電源:單電源 電壓 - 電源，單路/雙路(±):2.7 V ~ 5.5 V 電流 - 電源:5µA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:托盤
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