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參數(shù)資料
| 型號： | ADUuC7027BSTZ62-RL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 中文描述： | 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器 |
| 文件頁數(shù)： | 55/92頁 |
| 文件大?。?/td> | 850K |
| 代理商： | ADUUC7027BSTZ62-RL |
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ADuC7019/20/21/22/24/25/26/27
Three-Phase Timing Unit
PWM Switching Frequency (PWMDAT0 MMR)
The PWM switching frequency is controlled by the PWM
period register, PWMDAT0. The fundamental timing unit of
the PWM controller is
t
CORE
= 1/
f
CORE
Rev. A | Page 55 of 92
where
f
CORE
is the core frequency of the MicroConverter.
Therefore, for a 41.78 MHz
f
CORE
, the fundamental time
increment is 24 ns. The value written to the PWMDAT0
register is effectively the number of
f
CORE
clock increments in
a PWM period. The required PWMDAT0 value is a function of
the desired PWM switching frequency (
f
PWN
) and is given by
PWMDAT0
=
f
CORE
/(2 ×
f
PWM
)
Therefore, the PWM switching period,
T
S
, can be written as
T
S
= 2 ×
PWMDAT0
×
t
CORE
The largest value that can be written to the 16-bit PWMDAT0
MMR is 0×FFFF = 65535, which corresponds to a minimum
PWM switching frequency of
f
PWM(min)
= 41.78 × 10
6
/(2 × 65535) = 318.75 Hz
Note that a PWMDAT0 value of 0 and 1 are not defined and
should not be used.
PWM Switching Dead Time (PWMDAT1 MMR)
The second important parameter that must be set up in the initial
configuration of the PWM block is the switching dead time. This
is a short delay time introduced between turning off one PWM
signal (0H, for example) and turning on the complementary
signal (0L). This short time delay is introduced to permit the
power switch to be turned off (in this case, 0H) to completely
recover its blocking capability before the complementary switch is
turned on. This time delay prevents a potentially destructive
short-circuit condition from developing across the dc link
capacitor of a typical voltage source inverter.
The dead time is controlled by the 10-bit, read/write PWMDAT1
register. There is only one dead-time register that controls the
dead time inserted into all three pairs of PWM output signals.
The dead time,
TD
, is related to the value in the PWMDAT1
register by:
TD
=
PWMDAT1
× 2 ×
t
CORE
Therefore, a
PWMDAT1
value of 0x00A (= 10), introduces
a 426 ns delay between the turn-off on any PWM signal (0H,
for example) and the turn-on of its complementary signal (0L).
The amount of the dead time can therefore be programmed in
increments of 2
t
CORE
(or 49 ns for a 41.78 MHz core clock).
The PWMDAT1 register is a 10-bit register with a maximum
value of 0x3FF (= 1023), which corresponds to a maximum
programmed dead time of
TD
(max)
= 1023 × 2 ×
t
CORE
= 1023 × 2 × 24 ×10
–9
= 48.97 μs
for a core clock of 41.78 MHz
Obviously, the dead time can be programmed to be zero by
writing 0 to the PWMDAT1 register.
PWM Operating Mode (PWMCON, PWMSTA MMRs)
As previously discussed, the PWM controller of the
ADuC7019/7020/7021/7022/7024/7025/7026/7027 can operate
in two distinct modes, single update mode and double update
mode. The operating mode of the PWM controller is
determined by the state of Bit 2 of the PWMCON register.
If this bit is cleared, the PWM operates in the single update
mode. Setting Bit 2 places the PWM in the double update
mode. The default operating mode is single update mode.
In single update mode, a single PWMSYNC pulse is produced
in each PWM period. The rising edge of this signal marks the
start of a new PWM cycle, and is used to latch new values from
the PWM configuration registers (PWMDAT0 and PWMDAT1)
and the PWM duty cycle registers (PWMCH0, PWMCH1, and
PWMCH2) into the three-phase timing unit. In addition, the
PWMEN register is latched into the output control unit on the
rising edge of the PWMSYNC pulse. In effect, this means that
the characteristics and resulting duty cycles of the PWM signals
can be updated only once per PWM period at the start of each
cycle. The result is symmetrical PWM patterns about the
midpoint of the switching period.
In double update mode, there is an additional PWMSYNC
pulse produced at the midpoint of each PWM period. The
rising edge of this new PWMSYNC pulse is again used to latch
new values of the PWM configuration registers, duty cycle
registers, and the PWMEN register. As a result, it is possible to
alter both the characteristics (switching frequency and dead
time) as well as the output duty cycles at the midpoint of each
PWM cycle. Consequently, it is also possible to produce PWM
switching patterns that are no longer symmetrical about the
midpoint of the period (asymmetrical PWM patterns). In
double update mode, it may be necessary to know whether
operation at any point in time is in either the first half or the
second half of the PWM cycle. This information is provided by
Bit 0 of the PWMSTA register, which is cleared during
operation in the first half of each PWM period (between the
rising edge of the original PWMSYNC pulse and the rising edge
of the new PWMSYNC pulse introduced in double update
mode). Bit 0 of the PWMSTA register is set during operation
in the second half of each PWM period. This status bit allows
the user to make a determination of the particular half-cycle
during implementation of the PWMSYNC interrupt service
routine, if required.
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