參數(shù)資料
型號(hào)： ADUM3201CRZ-RL7
廠商： ANALOG DEVICES INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： Dual-Channel, Digital Isolators, Enhanced System-Level ESD Reliability
中文描述： SPECIALTY ANALOG CIRCUIT, PDSO8
封裝： ROHS COMPLIANT, MS-012AA, SOIC-8
文件頁(yè)數(shù)： 15/20頁(yè)
文件大?。?/td> 222K
代理商： ADUM3201CRZ-RL7
ADuM3200/ADuM3201
APPLICATION INFORMATION
PC BOARD LAYOUT
The ADuM320x digital isolators require no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins. The
capacitor value should be between 0.01 μF and 0.1 μF. The total
lead length between both ends of the capacitor and the input
power supply pin should not exceed 20 mm.
Rev. 0 | Page 15 of 20
SYSTEM-LEVEL ESD CONSIDERATIONS AND
ENHANCEMENTS
System-level ESD reliability (for example, per IEC 61000-4-x)
is highly dependent on system design which varies widely by
application. The ADuM320x incorporate many enhancements
to make ESD reliability less dependent on system design. The
enhancements include:
ESD protection cells added to all input/output interfaces.
Key metal trace resistances reduced using wider geometry
and paralleling of lines with vias.
The SCR effect inherent in CMOS devices minimized by use
of guarding and isolation technique between PMOS and
NMOS devices.
Areas of high electric field concentration eliminated using
45° corners on metal traces.
Supply pin overvoltage prevented with larger ESD clamps
between each supply pin and its respective ground.
While the ADuM320x improve system-level ESD reliability,
they are no substitute for a robust system-level design. See
Application Note AN-793, ESD/Latch-Up Considerations with
i
Coupler Isolation Products
for detailed recommendations on
board layout and system-level design.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output can differ from the propagation
delay to a logic high.
INPUT (V
IX
)
OUTPUT (V
OX
)
t
PLH
t
PHL
50%
50%
0
Figure 12. Propagation Delay Parameters
Pulse-width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the input signal’s timing is preserved.
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM320x component.
Propagation delay skew refers to the maximum amount that the
propagation delay differs between multiple ADuM320x
components operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is therefore either set or reset by the
pulses, indicating input logic transitions. In the absence of logic
transitions of more than 2 μs at the input, a periodic set of
refresh pulses indicative of the correct input state are sent to
ensure dc correctness at the output. If the decoder receives no
internal pulses for more than about 5 μs, the input side is
assumed to be unpowered or nonfunctional, in which case,
the isolator output is forced to a default state (see Table 8) by
the watchdog timer circuit.
The ADuM320x are extremely immune to external magnetic
fields. The limitation on the ADuM320x’s magnetic field
immunity is set by the condition in which induced voltage in
the transformer’s receiving coil is sufficiently large to either
falsely set or reset the decoder. The following analysis defines
the conditions under which this can occur. The 3 V operating
condition of the ADuM320x is examined because it represents
the most susceptible mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V,
therefore establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
V
= (dβ/
dt
) ∑π
r
n
2
,
n
= 1, 2, . . . ,
N
where:
β is the magnetic flux density (gauss).
N
is the number of turns in the receiving coil.
r
n
is the radius of the nth turn in the receiving coil (cm).
Given the geometry of the receiving coil in the ADuM320x and
an imposed requirement that the induced voltage be at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated, as shown in Figure 13.
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