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參數(shù)資料
| 型號(hào)： | ADUM3100 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Digital Isolator, Enhanced System-Level ESD Reliability |
| 中文描述： | 數(shù)字隔離器，提高其系統(tǒng)級(jí)靜電放電的可靠性 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 289K |
| 代理商： | ADUM3100 |
ADuM3100
APPLICATIONS
PC BOARD LAYOUT
The ADuM3100 digital isolator requires no external interface
circuitry for the logic interfaces. A bypass capacitor is
recommended at the input and output supply pins. The input
bypass capacitor can conveniently connect between Pin 3 and
Pin 4 (see Figure 12). Alternatively, the bypass capacitor can be
located between Pin 1 and Pin 4. The output bypass capacitor
can be connected between Pin 7 and Pin 8 or Pin 5 and Pin 8.
The capacitor value should be between 0.01 μF and 0.1 μF. The
total lead length between both ends of the capacitor and the
power supply pins should not exceed 20 mm.
Rev. A | Page 13 of 16
V
DD1
V
1
(DATA)
GND
1
V
DD2
V
O
(DATA OUT)
GND
2
(OPTIONAL)
0
Figure 12. Recommended Printed Circuit Board Layout
SYSTEM-LEVEL ESD CONSIDERATIONS AND
ENHANCEMENTS
System-level ESD reliability (for example, per IEC 61000-4-x)
is highly dependent on system design which varies widely by
application. The ADuM3100 incorporates many enhancements
to make ESD reliability less dependent on system design. The
enhancements include:
ESD protection cells added to all input/output interfaces.
Key metal trace resistances reduced using wider geometry
and paralleling of lines with vias.
The SCR effect inherent in CMOS devices minimized by use
of guarding and isolation technique between PMOS and
NMOS devices.
Areas of high electric field concentration eliminated using
45° corners on metal traces.
Supply pin overvoltage prevented with larger ESD clamps
between each supply pin and its respective ground.
While the ADuM3100 improves system-level ESD reliability, it
is no substitute for a robust system-level design. See
Application
Note AN-793, ESD/Latch-Up Considerations with
i
Coupler
Isolation Products
for detailed recommendations on board
layout and system-level design.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay time describes the length of time it takes for a
logic signal to propagate through a component. Propagation
delay time to logic low output and propagation delay time to
logic high output refer to the duration between an input signal
transition and the respective output signal transition
(see Figure 13).
INPUT (V
I
)
OUTPUT (V
O
)
t
PLH
t
PHL
50%
50%
0
Figure 13. Propagation Delay Parameters
Pulse-width distortion is the maximum difference between t
PLH
and t
PHL
and provides an indication of how accurately the input
signal timing is preserved in the component output signal.
Propagation delay skew is the difference between the minimum
and maximum propagation delay values among multiple
ADuM3100 components operated at the same operating
temperature and having the same output load.
Depending on the input signal rise/fall time, the measured
propagation delay based on the input 50% level can vary from
the true propagation delay of the component (as measured from
its input switching threshold). This is due to the fact that the
input threshold, as is the case with commonly used optocouplers,
is at a different voltage level than the 50% point of typical input
signals. This propagation delay difference is:
Δ
LH
=
t
′
PLH
t
PLH
= (
t
r
/0.8
V
I
)(0.5
V
1
V
ITH (L-H)
)
Δ
HL
= t
′
PHL
t
PHL
= (
t
f
/0.8
V
I
)(0.5
V
1
V
ITH (H-L)
)
where:
t
PLH
,
t
PHL
= propagation delays as measured from the input
50%.
t
′
PLH
,
t
′
PHL
= propagation delays as measured from the input
switching thresholds.
t
r
,
t
f
= input 10% to 90% rise/fall time.
V
I
= amplitude of input signal (0 to V
I
levels assumed).
V
ITH (L–H)
,
V
ITH (H–L)
= input switching thresholds.
Δ
LH
V
ITH(H–L)
INPUT (V
I
)
V
ITH(L–H)
V
I
Δ
HL
t
PHL
t'
PHL
t
PLH
t'
PLH
OUTPUT (V
O
)
50%
50%
0
Figure 14. Impact of Input Rise/Fall Time on Propagation Delay
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