參數(shù)資料
型號(hào)： ADuM1310ARWZ1
廠商： Analog Devices, Inc.
英文描述： Triple-Channel Digital Isolators
中文描述： 三通道數(shù)字隔離器
文件頁(yè)數(shù)： 18/20頁(yè)
文件大?。?/td> 282K
代理商： ADUM1310ARWZ1
ADuM1310/ADuM1311
APPLICATION INFORMATION
PC BOARD LAYOUT
The ADuM131x digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins (see
Figure 13). Bypass capacitors are most conveniently connected
between Pin 1 and Pin 2 for V
DD1
and between Pin 15 and Pin 16
for V
DD2
. The capacitor value should be between 0.01 μF and
0.1 μF. The total lead length between both ends of the capacitor
and the input power supply pin should not exceed 20 mm.
Bypassing between Pin 1 and Pin 8 and between Pin 9 and
Pin 16 should be considered, unless both of the ground pins on
each package are connected together close to the package.
Rev. F | Page 18 of 20
0
GND
1
V
DD1
GND
2
V
DD2
GND1
V
IA
GND
2
V
OA
V
IB
V
OB
V
IC
/V
OC
V
OC
/V
IC
NC
NC
CTRL
1
CTRL
2
Figure 13. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, care
should be taken to ensure that board coupling across the isolation
barrier is minimized. Furthermore, the board layout should be
designed such that any coupling that does occur equally affects
all pins on a given component side. Failure to ensure this can
cause voltage differentials between pins exceeding the device’s
absolute maximum ratings, thereby leading to latch-up or
permanent damage.
PROPAGATION DELAY
RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The input-to-
output propagation delay time for a high-to-low transition may
differ from the propagation delay time of a low-to-high transition.
0
INPUT (V
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
Figure 14. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the input signal’s timing is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM131x component.
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM131x
components operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent to the decoder via the
transformer. The decoder is bistable and is therefore either set
or reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than 2 μs, a
periodic set of refresh pulses indicative of the correct input state
are sent to ensure dc correctness at the output. If the decoder
receives no internal pulses of more than about 5 μs, the input
side is assumed to be unpowered or nonfunctional, in which
case the isolator output is forced to a default state (see Table 12)
by the watchdog timer circuit.
The magnetic field immunity of the ADuM131x is determined
by the changing magnetic field, which induces a voltage in the
transformer’s receiving coil large enough to either falsely set or
reset the decoder. The following analysis defines the conditions
under which this can occur. The 3 V operating condition of the
ADuM131x is examined because it represents the most suscep-
tible mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V The decoder has a sensing threshold at about 0.5 V thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
V
= (
d
β
/dt
)
∑
π
r
n2
; n
= 1, 2, … ,
N
where:
β is magnetic flux density (gauss).
N
is the number of turns in the receiving coil.
r
n
is the radius of the n
th
turn in the receiving coil (cm).
Given the geometry of the receiving coil in the ADuM131x and
an imposed requirement that the induced voltage be, at most,
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field at a given frequency can be calculated. The result
is shown in Figure 15.
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