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參數(shù)資料
| 型號： | ADUM1250 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Hot Swappable Dual I2C Isolators |
| 中文描述： | 熱插拔雙的I2C隔離器 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 201K |
| 代理商： | ADUM1250 |
ADuM1250/ADuM1251
APPLICATION NOTES
FUNCTIONAL DESCRIPTION
The ADuM1250/ADuM1251 interfaces on each side to a
bidirectional I
2
C signal. Internally, the I
2
C interface is split into
two unidirectional channels communicating in opposing
directions via a dedicated
i
Coupler isolation channel for each.
One channel (the bottom channel of each channel pair shown
in Figure 6) senses the voltage state of the Side 1 I
2
C pin and
transmits its state to its respective Side 2 I
2
C pin.
Both the Side 1 and the Side 2 I
2
C pins are designed to interface
to an I
2
C bus operating in the 3.0 V to 5.5 V range. A logic low
on either causes the opposite pin to be pulled low enough to
comply with the logic low threshold requirements of other I
2
C
devices on the bus. Avoidance of I
2
C bus contention is ensured
by an input low threshold at SDA
1
or SCL
1
guaranteed to be at
least 50 mV less than the output low signal at the same pin. This
prevents an output logic low at Side 1 being transmitted back to
Side 2 and pulling down the I
2
C bus.
Since the Side 2 logic levels/thresholds are standard I
2
C values,
multiple ADuM1250/ADuM1251 devices connected to a bus by
their Side 2 pins can communicate with each other and with
other devices having I
2
C compatibility
1
.
However, since the Side 1 pin has a modified output level/input
threshold, this side of the ADuM1250/ADuM1251 can only
communicate with devices conforming to the I
2
C standard. In
other words, Side 2 of the ADuM1250/ADuM1251 is I
2
C-
compliant while Side 1 is only I
2
C-compatible.
The output logic low levels are independent of the V
DD1
and
V
DD2
voltages. The input logic low threshold at Side 1 is also
independent of V
DD1
. However, the input logic low threshold at
Side 2 is designed to be at 0.3 V
DD2
, consistent with I
2
C
requirements. The Side 1 and Side 2 pins have open-collector
outputs whose high levels are set via pull-up resistors to their
respective supply voltages.
Rev. 0 | Page 10 of 12
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V
DD1
SDA
1
SCL
1
V
DD2
SDA
2
SCL
2
C
L
GND
2
1
2
3
8
7
6
0
5
GND
1
4
C
L
R2
R2
Figure 6. ADuM1250 Block Diagram
1
Here a distinction is made between I
2
C compatibility and I
2
C compliance. I
2
C
compatibility refers to situations in which a component's logic levels do not
necessarily meet the requirements of the I
2
C specification but still allow the
component to communication with an I
2
C-compliant device. I
2
C compliance
refers to situations in which a component's logic levels meet the
requirements of the I
2
C specification.
STARTUP
Both the V
DD1
and V
DD2
supplies have an under voltage lockout
feature to prevent the signal channels from operating unless
certain criteria are met. This avoids the possibility of input logic
low signals from pulling down the I
2
C bus inadvertently during
power-up/power-down.
The two criteria that must be met in order for the signal
channels to be enabled are as follows:
Both supplies must be at least 2.5 V.
At least 40 μs must elapse after both supplies exceeded the
internal startup threshold of 2.0 V.
Until both of these criteria are met for both supplies, the
ADuM1250/ADuM1251 outputs are pulled high, ensuring a
startup that avoids any disturbances on the bus. Figure 7 and
Figure 8 illustrate the supply conditions for fast and slow input
supply slew rates.
0
MINIMUM RECOMMENDED
OPERATING SUPPLY, 3.0V
MINIMUM VALID SUPPLY, 2.5V
INTERNAL STARTUP
THRESHOLD, 2.0V
40μs
SUPPLY VALID
Figure 7. Start-Up Condition, Supply Slew Rate >12.5 V/ms
0
40μs
SUPPLY VALID
MIN. RECOMMENDED
OPERATING SUPPLY, 3.0V
MIN. VALID SUPPLY, 2.5V
INTERNAL STARTUP
THRESHOLD, 2.0V
Figure 8. Start-Up Condition, Supply Slew Rate <12.5 V/ms
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