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參數(shù)資料
| 型號(hào)： | ADUM1100UR-RL7 |
| 廠(chǎng)商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | 通信及網(wǎng)絡(luò) |
| 英文描述： | iCoupler Digital Isolator |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO8 |
| 封裝： | MS-012AA, SOIC-8 |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大?。?/td> | 167K |
| 代理商： | ADUM1100UR-RL7 |
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REV. E
–5–
ADuM1100
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
SWITCHING SPECIFICATIONS (continued)
Propagation Delay Skew
(Equal Temperature, Supplies)
6, 8
5 V/3 V Operation
3 V/5 V Operation
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity at
Logic Low/High Output
8
t
PSK2
9
12
ns
ns
ns
C
L
= 15 pF, CMOS Signal Levels
C
L
= 15 pF, CMOS Signal Levels
C
L
= 15 pF, CMOS Signal Levels
t
R
, t
f
3
|CM
L
|,
|CM
H
|
C
PD1
25
35
kV/
μ
s
V
I
= 0 or V
DD1
, V
CM
= 1000 V,
Transient Magnitude = 800 V
Input Dynamic Power Dissipation Capacitance
10
5 V/3 V Operation
3 V/5 V Operation
Output Dynamic Power Dissipation Capacitance
10
5 V/3 V Operation
3 V/5 V Operation
35
47
pF
pF
C
PD2
8
14
pF
pF
NOTES
All voltages are relative to their respective ground.
2
Output supply current values are with no output load present. The supply current drawn at a given signal frequency when an output load is present is given by
I
=
I
+
V
×
f
×
C
, where
I
is the unloaded output supply current,
f
is the input signal frequency, and
C
L
is the output load capacitance.
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
t
is measured from the 50% level of the falling edge of the V
signal to the 50% level of the falling edge of the V
O
signal. t
PLH
is measured from the 50% level of
the rising edge of the V
signal to the 50% level of the rising edge of the V
signal.
6
Since the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width distortion
may be affected by slow input rise/fall times. See the Propagation Delay-Related Parameters
section and Figures 3 to 7 for information on the impact of given input
rise/fall times on these parameters.
7
Pulse width distortion change versus temperature is the absolute value of the change in pulse width distortion for a 1
°
C change in operating temperature.
8
t
is the magnitude of the worst-case difference in t
and/or t
that will be measured between units at the same operating temperature and output load within
the recommended operating conditions. t
is the magnitude of the worst-case difference in t
PHL
and/or t
PLH
that will be measured between units at the same operating
temperature, supply voltages, and output load within the recommended operating conditions.
9
CM
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
> 0.8 V
. CM
is the maximum common-mode voltage slew
rate that can be sustained while maintaining V
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the
range over which the common-mode is slewed.
10
The dynamic power dissipation capacitance is given by
C
= (
I
– I
)/(
V
×
f
), where
i
= 1 or 2 and
f
is the input signal frequency.
The supply current consumptions at a given frequency and output load are calculated as
I
DD
1
=
C
PD
1
×
V
DD
1
×
f
+
I
DD
1(
Q
)
;
I
DD
2(
L
)
= (
C
PD
2
+
C
L
)
×
V
DD
2
×
f
+
I
DD
2(
Q
)
, where
C
L
is the output load capacitance.
Specifications subject to change without notice.
PACKAGE CHARACTERISTICS
Parameter
Resistance (Input-Output)
1
Capacitance (Input-Output)
1
Input Capacitance
2
Input IC Junction-to-Case
Thermal Resistance
Output IC Junction-to-Case
Thermal Resistance
Package Power Dissipation
Symbol
Min
Typ
10
12
1
4.0
46
Max
Unit
pF
pF
°
C/W
Test Conditions
R
I–O
C
I–O
C
I
θ
JCI
f = 1 MHz
Thermocouple Located at Center
Underside of Package
θ
JCO
41
°
C/W
P
PD
240
mW
NOTES
1
Device considered a 2-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together.
2
Input capacitance is measured at Pin 2 (V
I
).
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