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| 型號： | ADUC842BCPZ8-5 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 59/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8KB FLASH ADC/DAC 56LFCSP |
| 標準包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16.78MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設備： | DMA，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.75 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 包裝： | 托盤 |
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ADuC841/ADuC842/ADuC843
Rev. 0 | Page 62 of 88
TIMER/COUNTER 0 AND 1 OPERATING MODES
The following sections describe the operating modes for
Timer/Counters 0 and 1. Unless otherwise noted, assume that
these modes of operation are the same for both Timer 0 and
Timer 1.
Mode 0 (13-Bit Timer/Counter)
Mode 0 configures an 8-bit timer/counter. Figure 66 shows
Mode 0 operation. Note that the divide-by-12 prescaler is not
present on the single-cycle core.
CORE
CLK
P3.4/T0
P3.2/INT0
TR0
TF0
TH0
(8 BITS)
INTERRUPT
Tl0
(5 BITS)
CONTROL
GATE
C/T = 1
C/T = 0
03260-0-064
Figure 66. Timer/Counter 0, Mode 0
In this mode, the timer register is configured as a 13-bit register.
As the count rolls over from all 1s to all 0s, it sets the timer
overflow flag, TF0. TF0 can then be used to request an interrupt.
The counted input is enabled to the timer when TR0 = 1 and
either Gate = 0 or INT0 = 1. Setting Gate = 1 allows the timer to
be controlled by external input INT0 to facilitate pulse-width
measurements. TR0 is a control bit in the special function
register TCON; Gate is in TMOD. The 13-bit register consists of
all 8 bits of TH0 and the lower five bits of TL0. The upper 3 bits
of TL0 are indeterminate and should be ignored. Setting the run
flag (TR0) does not clear the registers.
Mode 1 (16-Bit Timer/Counter)
Mode 1 is the same as Mode 0, except that the Mode 1 timer
register is running with all 16 bits. Mode 1 is shown in
Figure 67.
CORE
CLK
CONTROL
P3.4/T0
GATE
TR0
TF0
TL0
(8 BITS)
TH0
(8 BITS)
INTERRUPT
P3.2/INT0
C/ T = 0
C/ T = 1
03260-0-066
Figure 67. Timer/Counter 0, Mode 1
Mode 2 (8-Bit Timer/Counter with Autoreload)
Mode 2 configures the timer register as an 8-bit counter (TL0)
with automatic reload, as shown in Figure 68. Overflow from TL0
not only sets TF0, but also reloads TL0 with the contents of TH0,
which is preset by software. The reload leaves TH0 unchanged.
CONTROL
TF0
TL0
(8 BITS)
INTERRUPT
RELOAD
TH0
(8 BITS)
CORE
CLK
P3.4/T0
GATE
TR0
P3.2/INT0
C/ T = 0
C/ T = 1
03260-
0-
067
Figure 68. Timer/Counter 0, Mode 2
Mode 3 (Two 8-Bit Timer/Counters)
Mode 3 has different effects on Timer 0 and Timer 1. Timer 1 in
Mode 3 simply holds its count. The effect is the same as setting
TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two
separate counters. This configuration is shown in Figure 69. TL0
uses the Timer 0 control bits: C/T, Gate, TR0, INT0, and TF0.
TH0 is locked into a timer function (counting machine cycles)
and takes over the use of TR1 and TF1 from Timer 1. Thus,
TH0 now controls the Timer 1 interrupt. Mode 3 is provided for
applications requiring an extra 8-bit timer or counter.
When Timer 0 is in Mode 3, Timer 1 can be turned on and off
by switching it out of and into its own Mode 3, or it can still be
used by the serial interface as a baud rate generator. In fact, it
can be used in any application not requiring an interrupt from
Timer 1 itself.
CONTROL
TF0
TL0
(8 BITS)
INTERRUPT
CORE
CLK
P3.4/T0
GATE
TR0
TF1
TH0
(8 BITS)
INTERRUPT
CORE
CLK/12
TR1
P3.2/INT0
C/ T = 0
C/ T = 1
03260-0-068
Figure 69. Timer/Counter 0, Mode 3
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