參數(shù)資料
型號： ADUC816BCP
廠商： Analog Devices Inc
文件頁數(shù)： 50/68頁
文件大小： 0K
描述： IC MCU 8K FLASH ADC/DAC 56LFCSP
標準包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： I²C，SPI，UART/USART
外圍設備： PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 8KB（8K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 640 x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 7x16b; D/A 1x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
包裝： 托盤
產(chǎn)品目錄頁面： 738 (CN2011-ZH PDF)
REV. 0
ADuC816
–54–
TIMER/COUNTER 0 AND 1 OPERATING MODES
The following paragraphs describe the operating modes for timer/
counters 0 and 1. Unless otherwise noted, it should be assumed
that these modes of operation are the same for timer 0 as for timer 1.
Mode 0 (13-Bit Timer/Counter)
Mode 0 configures an 8-bit timer/counter with a divide-by-32
prescaler. Figure 33 shows mode 0 operation.
12
CORE
CLK*
TF0
INTERRUPT
CONTROL
P3.4/T0
GATE
P3.2/
INT0
TR0
TL0
(5 BITS)
TH0
(8 BITS)
C/
T = 0
C/
T = 1
*THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42.
Figure 33. Timer/Counter 0, Mode 0
In this mode, the timer register is configured as a 13-bit register.
As the count rolls over from all 1s to all 0s, it sets the timer overflow
flag TF0. The overflow flag, TF0, can then be used to request an
interrupt. The counted input is enabled to the timer when TR0 = 1
and either Gate = 0 or
INT0 = 1. Setting Gate = 1 allows the timer
to be controlled by external input
INT0, to facilitate pulsewidth
measurements. TR0 is a control bit in the special function regis-
ter TCON; Gate is in TMOD. The 13-bit register consists of all
eight bits of TH0 and the lower five bits of TL0. The upper three
bits of TL0 are indeterminate and should be ignored. Setting the
run flag (TR0) does not clear the registers.
Mode 1 (16-Bit Timer/Counter)
Mode 1 is the same as Mode 0, except that the timer register is
running with all 16 bits. Mode 1 is shown in Figure 34.
12
CORE
CLK*
TF0
INTERRUPT
CONTROL
P3.4/T0
TL0
(8 BITS)
TH0
(8 BITS)
C/
T = 0
C/
T = 1
GATE
P3.2/
INT0
TR0
*THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42.
Figure 34. Timer/Counter 0, Mode 1
Mode 2 (8-Bit Timer/Counter with Autoreload)
Mode 2 configures the timer register as an 8-bit counter (TL0)
with automatic reload, as shown in Figure 35. Overflow from TL0
not only sets TF0, but also reloads TL0 with the contents of TH0,
which is preset by software. The reload leaves TH0 unchanged.
12
CORE
CLK*
CONTROL
P3.4/T0
TF0
TL0
(8 BITS)
INTERRUPT
C/
T = 0
C/
T = 1
RELOAD
TH0
(8 BITS)
GATE
P3.2/
INT0
TR0
*THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42.
Figure 35. Timer/Counter 0, Mode 2
Mode 3 (Two 8-Bit Timer/Counters)
Mode 3 has different effects on timer 0 and timer 1. Timer 1 in
Mode 3 simply holds its count. The effect is the same as setting
TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two
separate counters. This configuration is shown in Figure 36. TL0
uses the timer 0 control bits: C/T, Gate, TR0,
INT0, and TF0.
TH0 is locked into a timer function (counting machine cycles)
and takes over the use of TR1 and TF1 from timer 1. Thus, TH0
now controls the “timer 1” interrupt. Mode 3 is provided for
applications requiring an extra 8-bit timer or counter.
When timer 0 is in Mode 3, timer 1 can be turned on and off by
switching it out of, and into, its own Mode 3, or can still be used by
the serial interface as a Baud Rate Generator. In fact, it can be used,
in any application not requiring an interrupt from timer 1 itself.
12
CORE
CLK*
TL0
(8 BITS)
TF0
INTERRUPT
CONTROL
P3.4/T0
C/
T = 0
C/
T = 1
TH0
(8 BITS)
TF1
INTERRUPT
CORE
CLK/12
TR1
CORE
CLK/12
CONTROL
GATE
P3.2/
INT0
TR0
*THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42.
Figure 36. Timer/Counter 0, Mode 3
REV. A
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