參數(shù)資料
型號(hào): ADUC814ARU-REEL
廠商: ANALOG DEVICES INC
元件分類(lèi): 微控制器/微處理器
英文描述: MicroConverter, Small Package 12-Bit ADC with Embedded Flash MCU
中文描述: 8-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PDSO28
封裝: 4.40 X 9.70 MM, MO-153AE, TSSOP-28
文件頁(yè)數(shù): 56/72頁(yè)
文件大?。?/td> 846K
代理商: ADUC814ARU-REEL
ADuC814
Timer 2 Generated Baud Rates
Baud rates can also be generated using Timer 2. Using Timer 2
is similar to using Timer 1 in that the timer must overflow 16
times before a bit is transmitted/received. Because Timer 2 has a
16-bit autoreload mode, a wide range of baud rates is possible
using Timer 2.
Rev. A | Page 56 of 72
Modes 1 and 3 Baud Rate
= (1/16) × (
Timer 2 Overflow Rate
)
Therefore, when Timer 2 is used to generate baud rates, the
timer increments every two clock cycles and not every core
machine cycle as before. Therefore, it increments six times faster
than Timer 1, and therefore baud rates six times faster are
possible. Because Timer 2 has 16-bit autoreload capability, very
low baud rates are still possible. Timer 2 is selected as the baud
rate generator by setting the CLK and/or RCLK in T2CON. The
baud rates for transmit and receive can be simultaneously
different. Setting RCLK and/or TCLK puts Timer 2 into its baud
rate generator mode as shown in Figure 53.
In this case, the baud rate is given by the formula
Modes 1 and 3 Baud Rate
= (
Core Clk
)/
(32 × [65536 – (
RCAP2H
,
RCAP2L
)])
Table 28 shows some commonly used baud rates and how they
could be calculated from a core clock frequency of 2.0971 MHz
and 16.7772 MHz.
Table 28. Commonly Used Baud Rates, Timer 2
Ideal
Baud
CLK
Value
19200
16.78
–1 (FFH)
9600
16.78
–1 (FFH)
2400
16.78
–1 (FFH)
1200
16.78
–2 (FEH)
9600
2.10
–1 (FFH)
2400
2.10
–1 (FFH)
1200
2.10
–1 (FFH)
Core
RCAP2H
RCAP2L
Value
–27 (E5H)
–55 (C9H)
–218 (26H)
–181 (4BH)
–7 (FBH)
–27 (ECH)
–55 (D7H)
Actual
Baud
19418
9532
2405
1199
9362
2427
1191
%
Error
1.14
0.7
0.21
0.02
2.4
1.14
0.7
CORE
CLK*
÷2
÷2
÷16
÷16
TR2
CONTROL
RELOAD
TL2
(8 BITS)
TL2
(8 BITS)
EXEN2
CONTROL
NOTE: AVAILABILITY OF ADDITIONAL
EXTERNAL INTERRUPT
NOTE: OSCILLATOR FREQUENCY IS DIVIDED BY 2, NOT 12
TRANSITION
DETECTOR
T2EX
PIN
T2
PIN
RCAP2L
RCAP2H
C/T2 = 1
C/T2 = 0
*THE CORE CLOCK IS THE OUTPUT OF THE PLL
0
RCLK
TCLK
RX
CLOCK
TX
CLOCK
0
0
1
1
1
0
SMOD
TIMER 2
OVERFLOW
TIMER 1
OVERFLOW
EXF 2
TIMER 2
INTERRUPT
Figure 53. Timer 2, UART Baud Rates
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