參數(shù)資料
型號(hào)： ADUC7122BBCZ-RL
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 44/96頁(yè)
文件大?。?/td> 0K
描述： PRECISION ANALOG MCU I.C
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 41.78MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 126KB（63K x 16）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 13x12b，D/A 12x12b
振蕩器型： 內(nèi)部
工作溫度： -10°C ~ 95°C
封裝/外殼： 108-LFBGA，CSPBGA
包裝： 標(biāo)準(zhǔn)包裝
其它名稱(chēng)： ADUC7122BBCZ-RLDKR
ADuC7122
Rev. 0 | Page 49 of 96
DIGITAL PERIPHERALS
PWM GENERAL OVERVIEW
The ADuC7122 integrates a 6-channel PWM interface. The
PWM outputs can be configured to drive an H-bridge or can be
used as standard PWM outputs. On power-up, the PWM outputs
default to H-bridge mode. This ensures that the H-bridge
controlled motor is turned off by default. In standard PWM
mode, the outputs are arranged as three pairs of PWM pins.
Users have control over the period of each pair of outputs and
over the duty cycle of each individual output.
Table 77. PWM MMRs
Name
Function
PWMCON1
PWM control
PWM1COM1
Compare Register 1 for PWM Output 1 and Output 2
PWM1COM2
Compare Register 2 for PWM Output 1 and Output 2
PWM1COM3
Compare Register 3 for PWM Output 1 and Output 2
PWM1LEN
Frequency control for PWM Output 1 and Output 2
PWM2COM1
Compare Register 1 for PWM Output 3 and Output 4
PWM2COM2
Compare Register 2 for PWM Output 3 and Output 4
PWM2COM3
Compare Register 3 for PWM Output 3 and Output 4
PWM2LEN
Frequency control for PWM Output 3 and Output 4
PWM3COM1
Compare Register 1 for PWM Output 5 and Output 6
PWM3COM2
Compare Register 2 for PWM Output 5 and Output 6
PWM3COM3
Compare Register 3 for PWM Output 5 and Output 6
PWM3LEN
Frequency control for PWM Output 5 and Output 6
PWMCON2
PWM convert start control
PWMICLR
PWM interrupt clear
In all modes, the PWMxCOMx MMRs control the point at
which the PWM outputs change state. An example of the first pair
of PWM outputs (PWM1 and PWM2) is shown in Figure 32.
HIGH SIDE
(PWM1)
LOW SIDE
(PWM2)
PWM1COM3
PWM1COM2
PWM1COM1
PWM1LEN
0
87
55
-0
33
Figure 32. PWM Timing
The PWM clock is selectable via PWMCON1 with UCLK divided
by one of the following values: 2, 4, 8, 16, 32, 64, 128, or 256.
The length of a PWM period is defined by PWMxLEN.
The PWM waveforms are set by the count value of the 16-bit
timer and the compare registers contents, as shown in the
PWM1 and PWM2 waveforms in Figure 32.
The low-side waveform, PWM2, goes high when the timer
count reaches PWM1LEN, and it goes low when the timer
count reaches the value held in PWM1COM3 or when the
high-side waveform PWM1 goes low.
The high-side waveform, PWM1, goes high when the timer
count reaches the value held in PWM1COM1, and it goes low
when the timer count reaches the value held in PWM1COM2.
In H-bridge mode, HMODE = 1 and Table 78 determine the
PWM outputs.
Table 78. PWMCON1 MMR Bit Designations (Address = 0xFFFF0F80, Default Value = 0x0012)
Bit
Name
Description
15
Reserved
This bit is reserved.
14
SYNC
Enables PWM synchronization.
Set to 1 by the user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low
transition on the SYNC pin.
Cleared by the user to ignore transitions on the SYNC pin.
13
PWM6INV
Set to 1 by the user to invert PWM6.
Cleared by the user to use PWM6 in normal mode.
12
PWM4NV
Set to 1 by the user to invert PWM4.
Cleared by the user to use PWM4 in normal mode.
11
PWM2INV
Set to 1 by the user to invert PWM2.
Cleared by the user to use PWM2 in normal mode.
10
PWMTRIP
Set to 1 by the user to enable PWM trip interrupt. When the PWMTRIP input is low, the PWMEN bit is cleared and an
interrupt is generated.
Cleared by the user to disable the PWMTRIP interrupt.
9
ENA
If HOFF = 0 and HMODE = 1.
Set to 1 by the user to enable PWM outputs.
Cleared by the user to disable PWM outputs.
If HOFF = 1 and HMODE = 1, see Table 79.
If not in H-Bridge mode, this bit has no effect.
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