參數(shù)資料
型號(hào)： ADSP2186
廠商： Analog Devices, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DSP Microcomputer
中文描述： DSP微機(jī)
文件頁(yè)數(shù)： 2/32頁(yè)
文件大小： 293K
代理商： ADSP2186
ADSP-2186
–2–
REV. 0
biased rounding, result free ALU operations, I/O memory trans-
fers and global interrupt masking for increased flexibility.
Fabricated in a high speed, double metal, low power, CMOS
process, the ADSP-2186 operates with a 30 ns instruction cycle
time. Every instruction can execute in a single processor cycle.
T he ADSP-2186’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera-
tions in parallel. In one processor cycle the ADSP-2186 can:
Generate the next program address
Fetch the next instruction
Perform one or two data moves
Update one or two data address pointers
Perform a computational operation
T his takes place while the processor continues to:
Receive and transmit data through the two serial ports
Receive and/or transmit data through the internal DMA port
Receive and/or transmit data through the byte DMA port
Decrement timer
Development System
T he ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, sup-
ports the ADSP-2186. T he System Builder provides a high level
method for defining the architecture of systems under develop-
ment. T he Assembler has an algebraic syntax that is easy to
program and debug. T he Linker combines object files into an
executable file. T he Simulator provides an interactive instruction-
level simulation with a reconfigurable user interface to display
different portions of the hardware environment. A PROM
Splitter generates PROM programmer compatible files. T he
C Compiler, based on the Free Software Foundation’s GNU
C Compiler, generates ADSP-2186 assembly source code.
T he source code debugger allows programs to be corrected in
the C environment. T he Runtime Library includes over 100
ANSI-standard mathematical and DSP-specific functions.
T he EZ-K IT Lite is a hardware/software kit offering a complete
development environment for the entire ADSP-21xx family: an
ADSP-218x based evaluation board with PC monitor software
plus Assembler, Linker, Simulator and PROM Splitter software.
T he ADSP-21xx EZ-K IT Lite is a low cost, easy to use hardware
platform on which you can quickly get started with your DSP soft-
ware design. T he EZ-K IT Lite includes the following features:
33 MHz ADSP-2181
Full 16-bit Stereo Audio I/O with AD1847 SoundPort
*
Codec
RS-232 Interface to PC with Microsoft
Windows 3.1
Control Software
EZ-ICE
* Connector for Emulator Control
DSP Demo Programs
T he ADSP-218x EZ-ICE
* Emulator aids in the hardware
debugging of an ADSP-2186 system. T he emulator consists of
hardware, host computer resident software, and the target board
connector. T he ADSP-2186 integrates on-chip emulation sup-
port with a 14-pin ICE-Port * interface. T his interface pro-
vides a simpler target board connection that requires fewer
mechanical clearance considerations than other ADSP-2100
Family EZ-ICE
*s. T he ADSP-2186 device need not be re-
moved from the target system when using the EZ-ICE
*, nor
are any adapters needed. Due to the small footprint of the
EZ-ICE
* connector, emulation can be supported in final board
designs.
T he EZ-ICE
* performs a full range of functions, including:
In-target operation
Up to 20 breakpoints
Single-step or full-speed operation
Registers and memory values can be examined and altered
PC upload and download functions
Instruction-level emulation of program booting and execution
Complete assembly and disassembly of instructions
C source-level debugging
See Designing An EZ-ICE
*-Compatible T arget System in the
ADSP-2100 Family EZ-Tools Manual
(ADSP-2181 sections), as
well as the T arget Board Connector for EZ-ICE
* Probe sec-
tion of this data sheet, for the exact specifications of the EZ-
ICE
* target board connector.
Additional Information
T his data sheet provides a general overview of ADSP-2186
functionality. For additional information on the architecture and
instruction set of the processor, refer to the
ADSP-2100 Family
User’s Manual
. For more information about the development
tools, refer to the
ADSP-2100 Family Development Tools Data
Sheet
.
ARCHIT E CT URE OVE RVIE W
T he ADSP-2186 instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single pro-
cessor cycle. T he ADSP-2186 assembly language uses an alge-
braic syntax for ease of coding and readability. A comprehensive
set of development tools supports program development.
SERIAL PORTS
SPORT 1
SPORT 0
MEMORY
PROGRAMMABLE
FI/O
BYTE DMA
CONTROLLER
8K 24
MEMORY
8K 16
MDATA
TIMER
ADSP-2100 BASE
ARCHITECTURE
SHIFTER
MAC
ALU
ARITHMETIC UNITS
PCONTROL
PROGRAM
SEQUENCER
DAG 2
DAG 1
DATA ADDRESS
GENERATORS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
EXDATA
BUS
ADDRESS
BUS
INTERNAL
DMA
PORT
EDATA
BUS
OR
FULL MEMORY
MODE
HOST MODE
Figure 1. Block Diagram
Figure 1 is an overall block diagram of the ADSP-2186. T he
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. T he
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. T he ALU per-
forms a standard set of arithmetic and logic operations; division
primitives are also supported. T he MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. T he shifter performs logical and arith-
metic shifts, normalization, denormalization and derive expo-
nent operations.
*SoundPort and E Z-ICE are registered trademarks of Analog Devices, Inc.
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